Flash memory controller and system including data pipelines incorporating multiple buffers

• US 8,738,841 B2
• Filed: 04/08/2008
• Issued: 05/27/2014
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Olbrich, Aaron K., Prins, Douglas A.
• Primary Examiner(s): Bradley, Matthew
• Assistant Examiner(s): Mercado, Ramon A
• Application Number:
  US12/082,220
• Publication Number:
  US 20090172260A1
• Time in Patent Office: 2,240 Days
• Field of Search: 711/5, 711/140, 711/147, 711/169, 710/317
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals

Abstract

A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.

Claims

1. A flash memory controller configured to be coupled to external flash memory devices, the flash memory controller comprising:

one or more ports for coupling to one or more host devices;

a set of flash stage buffers, each configured for holding a page of data read from one of the external flash memory devices pursuant to a respective host command, each flash stage buffer coupled to a respective external flash memory device by a first transmission path; and

a set of host port buffers configured for holding data read from a second set of buffers, the set of host port buffers coupled to the second set of buffers by a third transmission path and to the one or more host ports;

wherein the flash memory controller is further configured to be coupled to and control operation of an external data path RAM memory, the external data path RAM memory including the second set of buffers, the flash memory controller further configured to hold in the second set of buffers data read from any of the buffers in the set of flash stage buffers, the data stored in the second set of buffers related to a plurality of host commands, the flash memory controller further configured to couple the second set of buffers to the set of flash stage buffers by a second transmission path that includes a path through the external data path RAM memory.

2. The flash memory controller of claim 1, wherein the first transmission path is configured to transmit data at a first rate, and the second transmission path is configured to transmit data at a second, higher rate.

3. The flash memory controller of claim 1, wherein at least one of the set of flash stage buffers, the second set of buffers, and the set of host port buffers consists of a single buffer.

4. The flash memory controller of claim 1, wherein the flash memory controller is further configured to aggregate, in the second set of buffers, data read from two or more of the buffers in the set of flash stage buffers, wherein aggregating data includes aggregating data corresponding to a respective host command with other data corresponding to the respective host command.

5. The flash memory controller of claim 4, wherein the flash memory controller is further configured to transfer, from the second set of buffers, aggregated data corresponding to the respective host command to a respective host port buffer of the set of host port buffers subsequent to the second set of buffers receiving all data related to the respective host command.

6. The flash memory controller of claim 1, wherein the flash memory controller is further configured to store, in the second set of buffers, data read from any subset of the buffers in the set of flash stage buffers in logical block address order.

7. The flash memory controller of claim 1, wherein the data read from any of the buffers in the set of flash stage buffers correspond to data related to one or more host commands.

8. The flash memory controller of claim 1, wherein the flash memory controller is further configured to store, in the second set of buffers, data related to a plurality of host commands, wherein data related to a respective host command includes all data requested by the respective host command.

9. A system including a flash memory controller, an external data path RAM memory coupled to the flash memory controller, the flash memory controller coupled to external flash memory devices, the system configured for pipelined execution of host commands, the system comprising:

one or more ports for coupling to one or more host devices;

a set of flash stage buffers, each configured for holding a page of data read from one of the external flash memory devices pursuant to a respective host command, each flash stage buffer coupled to a respective external flash memory device by a first transmission path;

a second set of buffers in the external data path RAM memory, the second set of buffers configured for holding data read from any of the buffers in the set of flash stage buffers, the data stored in the second set of buffers related to a plurality of host commands, the second set of buffers coupled to the set of flash stage buffers by a second transmission path that includes a path through the external data path RAM memory; and

a set of host port buffers configured for holding data read from the second set of buffers, the set of host port buffers coupled to the second set of buffers by a third transmission path and to the one or more host ports.

10. The system as in claim 9, in which:

the first transmission path is configured to transmit data at a first rate, and the second transmission path is configured to transmit data at a second, higher rate.

11. The system as in claim 9, wherein at least one of the set of flash stage buffers, the second set of buffers, and the set of host port buffers consists of a single buffer.

12. The system of claim 9, wherein the second set of buffers are further configured to aggregate data read from two or more of the buffers in the set of flash stage buffers, wherein aggregating data includes aggregating data corresponding to a respective host command with other data corresponding to the respective host command.

13. The system of claim 12, wherein the second set of buffers are further configured to transfer aggregated data corresponding to the respective host command to a respective host port buffer of the set of host port buffers subsequent to the second set of buffers receiving all data related to the respective host command.

14. The system of claim 9, wherein the second set of buffers are further configured to store data read from any subset of the buffers in the set of flash stage buffers in logical block address order.

15. The system of claim 9, wherein the data read from any of the buffers in the set of flash stage buffers correspond to data related to one or more host commands.

16. The system of claim 9, wherein the second set of buffers are further configured to store data related to a plurality of host commands, wherein data related to a respective host command includes all data requested by the respective host command.

17. A method of operating a system, the system including a flash memory controller, an external data path RAM memory coupled to the flash memory controller, the flash memory controller coupled to external flash memory devices, the system configured for pipelined execution of host commands, the method comprising:

for a set of flash stage buffers, for each respective flash stage buffer, reading data from one of the external flash memory devices pursuant to a respective host command, each flash stage buffer coupled to a respective external flash memory device by a first transmission path;

transferring data from any of the buffers in the set of flash stage buffers to a second set of buffers in the external data path RAM memory, the data stored in the second set of buffers related to a plurality of host commands, the second set of buffers coupled to the set of flash stage buffers by a second transmission path that includes a path through the external data path RAM memory; and

transferring data from the second set of buffers to a set of host port buffers, the set of host port buffers coupled to the second set of buffers by a third transmission path and to one or more host ports.

18. The method of claim 17, wherein the first transmission path is configured to transmit data at a first rate, and the second transmission path is configured to transmit data at a second, higher rate.

19. The method of claim 17, wherein at least one of the set of flash stage buffers, the second set of buffers, and the set of host port buffers consists of a single buffer.

20. The method of claim 17, wherein the second set of buffers are further configured to aggregate data read from two or more of the buffers in the set of flash stage buffers, wherein aggregating data includes aggregating data corresponding to a respective host command with other data corresponding to the respective host command.

21. The method of claim 20, wherein the second set of buffers are further configured to transfer aggregated data corresponding to the respective host command to a respective host port buffer of the set of host port buffers subsequent to the second set of buffers receiving all data related to the respective host command.

22. The method of claim 17, wherein the second set of buffers are further configured to store data read from any subset of the buffers in the set of flash stage buffers in logical block address order.

23. The method of claim 17, wherein the data read from any of the buffers in the set of flash stage buffers correspond to data related to one or more host commands.

24. The method of claim 17, wherein the second set of buffers are further configured to store data related to a plurality of host commands, wherein data related to a respective host command includes all data requested by the respective host command.