Device and memory system for swappable memory

• US 8,738,851 B2
• Filed: 05/09/2013
• Issued: 05/27/2014
• Est. Priority Date: 03/28/2007
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kunimatsu, Atsushi, Nakai, Hiroto, Sakamoto, Hiroyuki, Maeda, Kenichi
• Primary Examiner(s): LANE, JOHN A
• Application Number:
  US13/890,891
• Publication Number:
  US 20130254471A1
• Time in Patent Office: 383 Days
• Field of Search: 711/103
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7211 Wear leveling

Abstract

An integrated memory management device according to an example of the invention comprises an acquiring unit acquiring a read destination logical address from a processor, an address conversion unit converting the read destination logical address into a read destination physical address of a non-volatile main memory, an access unit reading, from the non-volatile main memory, data that corresponds to the read destination physical address and has a size that is equal to a block size or an integer multiple of the page size of the non-volatile main memory, and transmission unit transferring the read data to a cache memory of the processor having a cache size that depends on the block size or the integer multiple of the page size of the non-volatile main memory.

Claims

1. A memory unit connectable to a host system comprising;

a substrate;

an interface unit formed to the substrate;

first and second non-volatile memory chips formed to the substrate; and

a memory management unit formed to the substrate and connected to the first and second non-volatile memory chips and the interface unit, the memory management unit comprising,

an access unit reading data from memory areas of the first and second non-volatile memory chips at reading, and writing data to the memory areas of the first and second non-volatile memory chips at writing,

wherein the first non-volatile memory chip is swappable when the second non-volatile memory chip is operating.

2. The memory unit according to claim 1, wherein the memory management unit comprises a RAID function.

3. The memory unit according to claim 1, wherein the memory management unit comprises an ECC function.

4. The memory unit according to claim 1, further comprising an alarm output unit which indicates conditions of the first and second non-volatile memory chips.

5. The memory unit according to claim 4, wherein the alarm output unit is an LED.

6. The memory unit according to claim 4, wherein the memory management unit causes the alarm output unit to indicate the conditions of the first and second non-volatile memory chips when the number of rewrite operations or read operations to the non-volatile memory chip reaches a predetermined threshold.

7. The memory unit according to claim 1, further comprising first and second alarm output units, each alarm output unit indicates a condition of a corresponding first and second non-volatile memory chip.

8. The memory unit according to claim 7, wherein the alarm output unit is an LED.

9. The memory unit according to claim 7, wherein the memory management unit causes the alarm output unit to indicate the condition of the non-volatile memory chip when the number of rewrite operations or read operations to the first and second non-volatile memory chips reaches a predetermined threshold.

10. The memory unit according to claim 7, further comprising first and second buttons, wherein when the first button is pushed, the memory management unit outputs a signal which prohibits an access to the first non-volatile memory chip.