Memory controller and a dynamic random access memory interface
First Claim
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1. A memory interface configured to communicate with a memory device, the memory interface comprising:
- a differential clock channel for transmitting a reference clock signal to the memory device;
a parallel command bus for transmitting one or more commands in parallcl from the memory interface to the memory device, wherein the parallel command bus does not require calibration on power-up; and
a serial address bus for transmitting one or more addresses to the memory device, wherein each address identifies a location within the memory device, and wherein, after a power-up operation but before the one or more addresses are transmitted via the serial address bus, the serial address bus is calibrated via a link training routine.
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Abstract
A memory controller and a dynamic random access memory (DRAM) interface are disclosed. The memory controller implements signals for the DRAM interface. The DRAM interface includes a differential clock signal, an uncalibrated parallel command bus, and a high-speed, serial address bus. The command bus may be used to initiate communication with the memory device upon power-up and to initiate calibration of the address bus.
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17 Claims
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1. A memory interface configured to communicate with a memory device, the memory interface comprising:
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a differential clock channel for transmitting a reference clock signal to the memory device; a parallel command bus for transmitting one or more commands in parallcl from the memory interface to the memory device, wherein the parallel command bus does not require calibration on power-up; and a serial address bus for transmitting one or more addresses to the memory device, wherein each address identifies a location within the memory device, and wherein, after a power-up operation but before the one or more addresses are transmitted via the serial address bus, the serial address bus is calibrated via a link training routine. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system comprising:
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a memory device; and a memory interface configured to communicate with the memory device, the memory interface including; a differential clock channel for transmitting a reference clock signal to the memory device, a parallel command bus for transmitting one or more commands from the memory interface to the memory device, wherein the parallel command bus does not require calibration on power-up; and a serial address bus for transmitting one or more addresses to the memory device, wherein each address identifies a location within the memory device, and wherein, after a power-up operation but before the one or more addresses are transmitted via the serial address bus, the serial address bus is calibrated via a link training routine. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A method for communicating with a memory device, the method comprising:
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transmitting a reference clock signal to the memory device via a differential clock channel; transmitting one or more commands from the memory interface to the memory device via a parallel command bus, wherein the parallel command bus does not require calibration on power-up; and transmitting one or more addresses to the memory device via a serial address bus, wherein each address identifies a location within the memory device, and after a power-up operation but before the one or more addresses are transmitted via the serial address bus, calibrating the serial address bus via a link training routine. - View Dependent Claims (15, 16, 17)
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Specification