Independent link and bank selection
First Claim
1. A memory device comprising:
- a first link and a second link;
a first bank and a second bank;
switching circuitry configured to switch data between the first bank, the second bank, the first link, and the second link, the switching circuitry comprising;
a first switching logic circuit comprising;
a first input for receiving a data input from the first link;
a second input for receiving an enable for writing for the first link;
a third input for receiving a data input from the second link;
a fourth input for receiving an enable for writing for the second link;
an output for outputting data to a memory bank.
8 Assignments
0 Petitions
Accused Products
Abstract
Provided is a memory system that has a plurality of memory banks and a plurality of link controllers. For each memory bank, there is first switching logic for receiving output for each link controller, and for passing on the output of only one of the link controllers to the memory bank. For each link controller, there is second switching logic for receiving an output of each memory bank, and for passing on the output of only one of the memory banks to the link controller. According to an embodiment of the invention, there is switch controller logic for controlling operation of both the first switching logic and the second switching logic to prevent simultaneous or overlapping access by multiple link controllers to the same memory bank, and for preventing simultaneous or overlapping access to multiple banks by the same link controller.
122 Citations
15 Claims
-
1. A memory device comprising:
-
a first link and a second link; a first bank and a second bank; switching circuitry configured to switch data between the first bank, the second bank, the first link, and the second link, the switching circuitry comprising; a first switching logic circuit comprising; a first input for receiving a data input from the first link; a second input for receiving an enable for writing for the first link; a third input for receiving a data input from the second link; a fourth input for receiving an enable for writing for the second link; an output for outputting data to a memory bank. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A memory device comprising:
-
a first link and a second link; a first bank and a second bank; switching circuitry configured to switch data between the first bank, the second bank, the first link, and the second link, the switching circuitry comprising; a switching logic circuit comprising; a first input for receiving a data input from the first bank; a second input for receiving an enable for reading from the first bank; a third input for receiving a data input from the second bank; a fourth input for receiving an enable for reading from the second bank; an output for outputting data read from the first or second bank. - View Dependent Claims (13, 14, 15)
-
Specification