Using non-lossless compression to save power

• US 8,738,945 B2
• Filed: 03/23/2011
• Issued: 05/27/2014
• Est. Priority Date: 12/12/2005
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Reed, David G.
• Primary Examiner(s): YANCHUS III, PAUL B
• Application Number:
  US13/069,387
• Publication Number:
  US 20110173476A1
• Time in Patent Office: 1,161 Days
• Field of Search: 713/300, 713/310, 713/320, 713/323, 713/324
• US Class Current: 713/320
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Circuits, methods, and systems that reduce or eliminate the number of data transfers between a system memory and a graphics processor under certain conditions. After inactivity by a user of an electronic device is detected, the color fidelity of pixels being displayed is reduced. Color fidelity can be reduced by compressing pixel values, and the compression may be non-lossless, for example, pixel data bits may be truncated. The degree of compression can be progressively increased for longer durations of inactivity, and this progression may be limited by a threshold. Inactivity may be detected by a lack of input from devices such as a keyboard, pen, mouse, or other input device. Once activity is resumed, uncompressed pixel data, or pixel data that is compressed in a lossless manner, is displayed.

Claims

1. A method of reducing power dissipation comprising:

with a graphics processor;

monitoring user activity;

if a first duration passes without user activity occurring, then

reading a plurality of pixels from an external memory;

reducing a color fidelity of the plurality of pixels;

storing the plurality of pixels having the reduced color fidelity in the external memory; and

displaying the plurality of pixels having the reduced color fidelity;

then

reading the plurality of pixels having the reduced color fidelity from the external memory; and

displaying the plurality of pixels having the reduced color fidelity; and

if a second duration passes without user activity, the second duration longer than the first duration, then

further reducing the color fidelity of the plurality of pixels;

storing the plurality of pixels having the further reduced color fidelity in a memory on the graphics processor; and

displaying the plurality of pixels having the further reduced color fidelity;

otherwise,

not reducing the color fidelity of the plurality of pixels; and

displaying the plurality of pixels.

2. The method of claim 1 wherein the color fidelity of the plurality of pixels is reduced using a non-lossless compression algorithm.

3. The method of claim 1 wherein the color fidelity of the plurality of pixels is reduced by truncating a value of each of the plurality of pixels.

4. The method of claim 1 further comprising:

if a second duration passes without user activity, the second duration longer than the first duration;

then

reducing a power supply for a central processing unit.

19. The method of claim 1 wherein the pixel values are compressed using a first algorithm and further compressed using a second algorithm.

5. An integrated circuit comprising:

a graphics processing unit comprising;

a first circuit configured to detect user activity;

a second circuit configured to compress pixel data; and

an internal memory to store compressed data; and

an external memory configured to store compressed pixel data and coupled to the graphics processing unit;

wherein when the first circuit detects user inactivity for a first duration, the second circuit compresses pixel data using a first algorithm,

wherein when the first circuit detects user inactivity for the first duration, and compressed pixel data is stored in the internal memory, compressed pixel data is read from the internal memory and displayed,

wherein when the first circuit detects user inactivity for the first duration, and compressed pixel data is stored in the external memory and not the internal memory, compressed pixel data is read from the external memory and displayed, and

wherein when the first circuit detects user inactivity for a second duration, the second circuit compresses pixel data using a second algorithm.

6. The integrated circuit of claim 5 wherein the first algorithm is non-lossless.

7. The integrated circuit of claim 5 wherein the first algorithm is to truncate pixel data bits.

8. The integrated circuit of claim 5 wherein when the first circuit detects user activity within the first duration, the second circuit does not compress pixel data using the first algorithm.

9. The integrated circuit of claim 5 wherein the integrated circuit is an Integrated Graphics Processor.

10. A method of reducing power dissipation by compressing pixel data comprising:

with a graphics processor;

detecting a user'"'"'s inactivity;

determining whether compressed pixel values are stored in an external memory; and

if they are not stored in the external memory then

receiving a first plurality of pixel values from the external memory;

compressing the pixel values;

storing the compressed pixel values in the external memory; and

if they are stored in the external memory then

determining whether compressed pixel values are stored in an internal memory on the graphics processor; and

if they are not stored in the internal memory, then

receiving the compressed pixel values from the external memory;

further compressing the compressed pixel values

storing the further compressed pixel values in the internal memory; and

displaying the further compressed pixel values, and if they are stored in the internal memory, then

reading the compressed pixel values from the internal memory; and

displaying the compressed pixel values.

11. The method of claim 10 wherein the compressed pixel values comprise a plurality of lines of an image frame.

12. The method of claim 10 wherein the compressed pixel values comprise an image frame.

13. The method of claim 12 further comprising:

reducing a power supply for a central processing unit.

14. The method of claim 10 wherein the pixel values are compressed by truncating bits of the pixel values.

15. The method of claim 10 wherein the inactivity is detected by monitoring activity on one or more input devices.

16. The method of claim 10 wherein the external memory is a system memory.

17. The method of claim 16 wherein the graphics processing unit is located on an integrated graphics processor.

18. The method of claim 10 further comprising:

detecting activity by the user;

receiving a second plurality of pixel values from the external memory; and

displaying the second plurality of pixel values.

20. The method of claim 10 wherein the pixel values are compressed using a first algorithm and further compressed using a second algorithm.