Memory device on the fly CRC mode

• US 8,738,993 B2
• Filed: 12/23/2010
• Issued: 05/27/2014
• Est. Priority Date: 12/06/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bains, Kuljit S.
• Primary Examiner(s): GUYTON, PHILIP A
• Application Number:
  US12/978,014
• Publication Number:
  US 20120144264A1
• Time in Patent Office: 1,251 Days
• Field of Search: 714/763, 714/800, 714/807
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1052 Bypassing or disabling error detection or correction
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
• CPC Class Codes: H03M 13/6505 Memory efficient implementations

Abstract

On the fly enabling and disabling of error detection for memory access transactions on a transaction basis is provided. Dynamic enabling and disabling of error detection for memory access transactions can also be applied for multiple transactions. Control logic associated with the memory device determines whether to apply error detection, and selectively enables error detection in the memory access transaction. The selective enabling of error detection in a memory access transaction can apply to either reads or writes.

Claims

1. A method comprising:

receiving a memory access command to implement a memory access transaction by a memory device from a memory controller, the memory access command including an inline error detection indicator generated by the memory controller, including one or more signal bits that specify within the memory access command whether to apply error detection for the memory access transaction;

determining whether to apply error detection for the memory access transaction based on the inline command where a separate determination is made for adjacent memory access transactions, the memory access transaction including a read operation or a write operation in response to a read command or a write command, respectively; and

selectively enabling error detection in the memory access transaction on a transaction basis based on the determination, where applying error detection adds data transfer overhead to the memory access transaction to provide an error check value.

2. The method of claim 1, wherein enabling error detection comprises enabling cyclic redundancy checking (CRC) through the use of a checksum value included in the memory access transaction data.

3. The method of claim 1, wherein enabling error detection on a transaction basis comprises enabling selection of different error detection states on back-to-back memory device access commands.

4. The method of claim 1, wherein enabling error detection on a transaction basis comprises enabling selection of different error detection states without using a mode register.

5. The method of claim 1, wherein enabling error detection on a transaction basis comprises sending an error detection enable command inline with a column access select (CAS) command.

6. The method of claim 5, wherein sending the error detection enable command inline with the CAS command comprises setting bits within the CAS command to selectively switch error detection on or off.

7. The method of claim 1, wherein error detection is selectively enabled based on a data type of a request for the memory access transaction.

8. The method of claim 7, wherein error detection is enabled for memory access transactions relating to system data or critical application data.

9. An apparatus comprising:

memory resources to store data; and

memory resource control logic coupled to the memory resources, the control logic to

receive a memory access command to implement a memory access transaction by a memory device from a memory controller, the memory access command including an inline error detection indicator generated by the memory controller, including one or more signal bits that specify within the memory access command whether to apply error detection for the memory access transaction;

determine whether to apply error detection for the memory access transaction based on the inline command where a separate determination is made for adjacent memory access transactions, the memory access transaction including a read operation or a write operation in response to a read command or a write command, respectively; and

selectively enable error detection in the memory access transaction on a transaction basis based on the determination, where applying error detection adds data transfer overhead to the memory access transaction to provide an error check value.

10. The apparatus of claim 9, wherein the memory resource control logic is to enable error detection by enabling cyclic redundancy checking (CRC) through the use of a checksum value included in the memory access transaction data.

11. The apparatus of claim 9, wherein the memory resource control logic is to enable error detection on a transaction basis by enabling selection of different error detection states on back-to-back memory device access commands.

12. The apparatus of claim 9, wherein the memory resource control logic is to enable error detection on a transaction basis by enabling selection of different error detection states without using a mode register.

13. The apparatus of claim 9, wherein the memory resource control logic is to enable error detection on a transaction basis by sending an error detection enable command inline with a column access select (CAS) command.

14. The apparatus of claim 13, wherein the memory resource control logic is to send the error detection enable command inline with the CAS command by setting bits within the CAS command to selectively switch error detection on or off.

15. The apparatus of claim 9, wherein error detection is selectively enabled based on a data type of a request for the memory access transaction.

16. The apparatus of claim 15, wherein error detection is enabled for memory access transactions relating to system data or critical application data.

17. A system comprising:

a memory device having

memory resources to store data; and

memory resource control logic coupled to the memory resources, the control logic to receive a memory access command to implement a memory access transaction by a memory device from a memory controller, the memory access command including an inline error detection indicator generated by the memory controller, including one or more signal bits that specify within the memory access command whether to apply error detection for the memory access transaction;

determine whether to apply error detection for the memory access transaction based on the inline command where a separate determination is made for adjacent memory access transactions, the memory access transaction including a read operation or a write operation in response to a read command or a write command, respectively; and

selectively enable error detection in the memory access transaction on a transaction basis based on the determination, where applying error detection adds data transfer overhead to the memory access transaction to provide an error check value; and

a multi-core processor coupled to the memory device to generate memory access requests for data stored on the memory device.

18. The system of claim 17, wherein the memory resource control logic is to enable error detection by enabling cyclic redundancy checking (CRC) through the use of a checksum value included in the memory access transaction data.

19. The system of claim 17, wherein the memory resource control logic is to enable error detection on a transaction basis by enabling selection of different error detection states on back-to-back memory device access commands.

20. The system of claim 17, wherein the memory resource control logic is to enable error detection on a transaction basis by enabling selection of different error detection states without using a mode register.

21. The system of claim 17, wherein the memory resource control logic is to enable error detection on a transaction basis by sending an error detection enable command inline with a column access select (CAS) command.

22. The system of claim 21, wherein the memory resource control logic is to send the error detection enable command inline with the CAS command by setting bits within the CAS command to selectively switch error detection on or off.

23. The system of claim 17, wherein error detection is selectively enabled based on a data type of a request from the multi-core processor.

24. The system of claim 23, wherein error detection is enabled for memory access transactions relating to system data or critical application data.

25. A method comprising:

receiving a memory access command to implement a memory access transaction by a memory device from a memory controller, the memory access command including an inline error detection indicator generated by the memory controller, including one or more signal bits that specify within the memory access command whether to apply error detection for the memory access transaction;

determining, during active operation of a memory device, whether to apply cyclic redundancy checking (CRC) to the memory access transaction based on the inline command where a separate determination is made for adjacent memory access transactions, the determination made on a transaction by transaction basis, the memory access transaction including a read operation or a write operation in response to a read command or a write command, respectively; and

selectively enabling CRC for the memory access transaction based on the determination by applying a setting to a mode register that controls a CRC mode for the memory device.

26. The method of claim 25, wherein selectively enabling CRC comprises enabling CRC for a series of transactions.

27. The method of claim 25, wherein selectively enabling CRC comprises selectively enabling CRC based on an amount of traffic to the memory device.