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Parallelizing non-countable loops with hardware transactional memory

  • US 8,739,141 B2
  • Filed: 05/19/2008
  • Issued: 05/27/2014
  • Est. Priority Date: 05/19/2008
  • Status: Active Grant
First Claim
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1. A method for parallelizing program code of an application, the method comprising:

  • examining one or more program instructions of a multi-threaded application;

    identifying a non-countable loop pattern, wherein the non-countable loop includes a first function that uses a loop index variable as a parameter, wherein the first function performs input/output and modifies data, wherein identifying the non-countable loop pattern comprises determining whether the non-countable loop pattern meets a set of conditions including;

    a) an iteration count of the non-countable loop pattern cannot be determined by a compiler;

    b) an exit condition function of the non-countable loop pattern does not modify the loop index variable; and

    c) the first function that uses the loop index variable as a parameter does not modify the loop index variable;

    if the non-countable loop pattern is determined to meet the set of conditions, replacing the non-countable loop pattern with a parallelized loop pattern, wherein the parallelized loop pattern is configured to squash and re-execute any speculative thread of the parallelized loop pattern that is signaled to have a transaction failure; and

    if the non-countable loop pattern is determined to not meet the set of conditions, compiling the non-countable loop to execute in a serial manner.

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