Stress in trigate devices using complimentary gate fill materials

• US 8,741,733 B2
• Filed: 01/25/2013
• Issued: 06/03/2014
• Est. Priority Date: 06/23/2008
• Status: Expired due to Fees

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Rakshit, Titash, Giles, Martin, Pillarisetty, Ravi, Kavalieros, Jack T.
• Primary Examiner(s): Karimy, Timor
• Application Number:
  US13/750,393
• Publication Number:
  US 20130143385A1
• Time in Patent Office: 494 Days
• Field of Search: 438/400
• US Class Current: 438/400
• CPC Class Codes: H01L 21/8234 MIS technology , i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 29/7845 the means being a conductive material, e.g. silicided S/D or Gate
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate transistor, thereby increasing the carrier mobility and operating frequency. Embodiments also contemplate method for use of the improved tri-gate device.

Claims

1. A method, comprising:

raising a first channel comprising an N-type material above a substrate, the first channel having a first top surface, a first pair of sidewalls, and a first current flow direction along a first major axis of the first channel;

raising a second channel comprising a P-type material above the substrate, the second channel having a second top surface, a second pair of sidewalls, and a second current flow direction along a second major axis of the second channel;

depositing a first gate around the first top surface and the first pair of sidewalls of the first channel and substantially perpendicular to the major axis, wherein the first gate comprises a first intrinsically stressed metal fill in which intrinsic stress of the first intrinsically stressed metal fill exerts a tensile stress upon the first channel such that charge carrier mobility in the first channel is improved in the first current flow direction; and

depositing a second gate around the second top surface and the second pair of sidewalls of the second channel and substantially perpendicular to the second major axis, wherein the second gate comprises a second intrinsically stressed metal fill in which intrinsic stress of the second intrinsically stressed metal fill exerts a compressive stress upon the second channel such that charge carrier mobility in the second channel is improved in the second current flow direction.

2. The method of claim 1, further comprising isolating the-first channel using a shallow trench isolation layer.

3. The method of claim 1, further comprising isolating the first channel, from the second channel, by using a shallow trench isolation layer.

4. The method of claim 1, wherein depositing the first gate comprises depositing an intrinsically compressively stressed copper metal fill that exerts the tensile stress upon the first channel such that the charge carrier mobility in the first channel is improved in the first current flow direction.

5. The method of claim 4, wherein depositing the second gate comprises depositing an intrinsically tensilely stressed tungsten metal fill that exerts the compressive stress upon the second channel such that the charge carrier mobility in the second channel is improved in the second current flow direction.