Semiconductor device and structure

• US 8,742,476 B1
• Filed: 11/27/2012
• Issued: 06/03/2014
• Est. Priority Date: 11/27/2012
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Sekar, Deepak, Cronquist, Brian
• Primary Examiner(s): Matthews, Colleen
• Assistant Examiner(s): Webb, Vernon P
• Application Number:
  US13/685,751
• Publication Number:
  US 20140145272A1
• Time in Patent Office: 553 Days
• Field of Search: 257/7, 257/275, 257/E29.286, 257/E21.614, 257/E27.026
• US Class Current: 257/275
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Claims

1. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors,

wherein said second transistors comprise mono-crystal,

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error,

wherein said mono-crystal comprises a first region and a second region which are horizontally oriented with respect to each other, said first region comprises a source or drain of said second transistor and said second region comprises a channel of said second transistor,

wherein said first region has substantially different dopant concentration than said second region, and

wherein said second transistors are gate replacement transistors.

2. The semiconductor device according to claim 1, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other side of said second layer than said at least one metal layer.

3. The semiconductor device according to claim 1, wherein said second layer is transferred using an ion-cut process.

4. The semiconductor device according to claim 1, wherein

said first transistors construct a plurality of first logic circuits, wherein

said second transistors construct a plurality of second logic circuits;

wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

5. The semiconductor device according to claim 1, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially greater said second metal layer.

6. The semiconductor device according to claim 1, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

7. The semiconductor device according to claim 1, wherein at least one of said second transistors is connected to another of said second transistors using one of said at least one metal layer.

8. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors, said second transistors comprising mono-crystal,

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error,

wherein said mono-crystal comprises a first region and a second region which are horizontally oriented with respect to each other, said first region comprises a source or drain of said second transistor and said second region comprises a channel of said second transistor,

wherein said first region has a different doping than said second region and

wherein said second transistors is a FinFet transistor.

9. The semiconductor device according to claim 8, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other side of said second layer than said at least one metal layer.

10. The semiconductor device according to claim 8, wherein said second layer is transferred using an ion-cut process.

11. The semiconductor device according to claim 8, wherein

said first transistors construct a plurality of first logic circuits, wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second layer logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

12. The semiconductor device according to claim 8, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially greater than said second metal layer.

13. The semiconductor device according to claim 8, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

14. The semiconductor device according to claim 8, wherein

said second transistors comprise P type transistors and N type transistors.

15. The semiconductor device according to claim 8, wherein at least one of said second transistors is connected to another of said second transistors using one of said at least one metal layer.

16. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors, said second transistors comprise mono-crystal,

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error,

wherein said mono-crystal comprises a first region and a second region which are horizontally oriented with respect to each other, said first region comprises a source or drain of said second transistor and said second region comprises a channel of said second transistor,

wherein said first region has a different doping than said second region and

wherein said second transistors is a Fully-depleted MOSFET transistor.

17. The semiconductor device according to claim 16, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other side of said second layer than said at least one metal layer.

18. The semiconductor device according to claim 16, wherein said second layer is transferred using an ion-cut process.

19. The semiconductor device according to claim 16, wherein

said first transistors construct a plurality of first logic circuits, wherein

said second transistors construct a plurality of second logic circuits;

wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

20. The semiconductor device according to claim 16, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially greater than said second metal layer.

21. The semiconductor device according to claim 16, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

22. The semiconductor device according to claim 16, wherein

said second transistors comprise P type transistors and N type transistors.

23. The semiconductor device according to claim 16, wherein at least one of said second transistors is connected to another of said second transistors using one of said at least one metal layer.

24. A semiconductor device comprising:

a first single crystal layer comprising first transistors, first alignment mark, and at least one metal layer, said at least one metal layer overlying said first single crystal layer,

wherein said at least one metal layer comprises copper or aluminum; and

a second layer overlying said at least one metal layer;

wherein said second layer comprises second transistors,

wherein said second transistors comprise mono-crystal,

wherein said second transistors are aligned to said first alignment mark with less than 40 nm alignment error,

wherein said mono-crystal comprises a first region and a second region which are horizontally oriented with respect to each other, said first region comprises a source or drain of said second transistor and said second region comprises a channel of said second transistor,

wherein said first region has a different dopant type than said second region, and

wherein said second transistors are gate replacement transistors.

25. The semiconductor device according to claim 24, wherein said second layer comprises a single crystal layer less than 0.4 micron thick, wherein the contacts to said second transistors are on the other side of said second layer than said at least one metal layer.

26. The semiconductor device according to claim 24, wherein said second layer is transferred using an ion-cut process.

27. The semiconductor device according to claim 24, wherein

said first transistors construct a plurality of first logic circuits, wherein

said second transistors construct a plurality of second logic circuits;

wherein

each logic circuit in said plurality of first logic circuits has at least one first output, wherein

each logic circuit in said plurality of second logic circuits has a second output, and wherein

said plurality of first transistors comprises a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.

28. The semiconductor device according to claim 24, wherein said at least one metal layer comprises a second metal layer overlaying a first metal layer, and wherein said first metal layer has a current carrying capacity substantially greater said second metal layer.

29. The semiconductor device according to claim 24, comprising a shielding structure designed to protect said at least one metal layer from being damaged by optical annealing of said second layer.

30. The semiconductor device according to claim 24, wherein at least one of said second transistors is connected to another of said second transistors using one of said at least one metal layer.