DRAM arrays

• US 8,742,483 B2
• Filed: 06/06/2012
• Issued: 06/03/2014
• Est. Priority Date: 05/17/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Fischer, Mark
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US13/490,369
• Publication Number:
  US 20120241832A1
• Time in Patent Office: 727 Days
• Field of Search: 257/68, 257/71, 257296-313, 257905-908, 257E27084-E27096, 257/E21.646, 365/222
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/05 Making the transistor

Abstract

The invention includes methods for utilizing partial silicon-on-insulator (SOI) technology in combination with fin field effect transistor (finFET) technology to form transistors particularly suitable for utilization in dynamic random access memory (DRAM) arrays. The invention also includes DRAM arrays having low rates of refresh. Additionally, the invention includes semiconductor constructions containing transistors with horizontally-opposing source/drain regions and channel regions between the source/drain regions. The transistors can include gates that encircle at least three-fourths of at least portions of the channel regions, and in some aspects can include gates that encircle substantially an entirety of at least portions of the channel regions.

Claims

1. A DRAM array, comprising:

a semiconductor substrate having a bulk semiconductor material with a thickness;

a vertical direction being defined to extend through the thickness, and a horizontal direction being defined to extend orthogonally to the vertical direction;

a plurality of transistors supported by the substrate;

each transistor comprising a gate containing electrically conductive gate material;

a channel proximate the gate; and

a pair of source/drain regions on opposing sides of the channel;

the source/drain regions and channel together forming a segment that extends primarily horizontally;

each transistor comprising a dielectric material between the gate material and the channel;

capacitors electrically coupled with source/drain regions of the transistors;

wherein each channel has a longitudinal axis from one of the source/drain regions to the other, and has a lateral periphery along a cross-section substantially orthogonal to the longitudinal axis;

wherein the lateral periphery is a four-sided polygon;

wherein the four-sided polygon of each channel has a bottom surface, a top surface, and a pair of side surfaces extending from the bottom surface to the top surface;

wherein the dielectric material of each transistor is conformally along and directly against the top and side surfaces of the four-sided polygon of the channel of the transistor, and extends under an entirety of the bottom surface, but is only directly against a portion of the bottom surface, and is not conformal to the bottom surface;

the dielectric material from one side of the polygon contacting the dielectric material from the other side of the polygon under the bottom surface; and

wherein the electrically conductive gate material of each transistor gate wraps around the lateral periphery of the channel and extends conformally along the dielectric material along the top and side surfaces of the four-sided polygon;

the electrically conductive gate material of each transistor gate also extending to under the bottom surface of the four-sided polygon, and being under an entirety of the bottom surface except for a region where the dielectric material from one side of the polygon contacts the dielectric material from the other side of the polygon.

2. The DRAM array of claim 1 wherein the bulk semiconductor material comprises monocrystalline silicon.

3. The DRAM array of claim 1 wherein the dielectric material of each transistor consists of silicon dioxide.

4. The DRAM array of claim 1 wherein the electrically conductive gate material comprises metal.