Apparatus and method for FinFETs

• US 8,742,509 B2
• Filed: 03/01/2012
• Issued: 06/03/2014
• Est. Priority Date: 03/01/2012
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Wu, Cheng-Hsien, Ko, Chih-Hsin, Lin, You-Ru, Wan, Cheng-Tien
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Lau, Christine C.
• Application Number:
  US13/410,073
• Publication Number:
  US 20130228875A1
• Time in Patent Office: 824 Days
• Field of Search: 257/240, 257/244, 257/259, 257/395, 257/396, 257/397, 257/401, 257/559, 257/E29.039, 257/E29.04, 257/E29.051, 257/E29.052, 257/E29.067, 257/E29.26, 257/E29.262, 257/E29.299, 257/374, 257/509, 257/510, 257/521, 257/524, 438/222
• US Class Current: 257/368
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02634 Homoepitaxy
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection

Abstract

A FinFET comprises an isolation region formed in a substrate, a cloak-shaped active region formed over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region. In addition, the FinFET comprises a gate electrode wrapping the channel of the cloak-shaped active region.

Claims

1. An apparatus comprising:

a first isolation region formed in a substrate, wherein the first isolation region has a first non-vertical sidewall;

a second isolation region formed in the substrate, wherein the second isolation region has a second non-vertical sidewall;

a V-shaped groove formed in the substrate, wherein the V-shaped groove, the first non-vertical sidewall and the second non-vertical sidewall form a cloak-shaped recess in the substrate;

a cloak-shaped active region formed in the cloak-shaped recess over the substrate, wherein the cloak-shaped active region has an upper portion protruding above a top surface of the isolation region, a first triangular region embedded in the first isolation region, a second triangular region embedded in the second isolation region and a V-shaped bottom portion, and wherein the cloak-shaped active region comprises;

a first drain/source region;

a second drain/source region; and

a channel between the first drain/source region and the second drain/source region; and

a gate electrode wrapping the channel of the cloak-shaped active region.

2. The apparatus of claim 1, further comprising:

a gate dielectric layer formed between the cloak-shaped active region and the gate electrode.

3. The apparatus of claim 1, wherein the cloak-shaped active region is formed of silicon germanium.

4. The apparatus of claim 1, wherein a turning point angle formed by the first non-vertical sidewall and the V-shaped groove is a range from about 130 degrees to about 160 degrees.

5. The apparatus of claim 1, wherein the first isolation region is a shallow trench isolation structure.

6. The apparatus of claim 1, wherein the V-shaped groove has an interior angle in a range from about 100 degrees to about 110 degrees.

7. The apparatus of claim 1, wherein the gate electrode, the first drain/source region, the second drain/source region and the channel form a FinFET.

8. A device comprising:

a first drain/source region formed in a substrate;

a second drain/source region formed in the substrate;

a channel between the first drain/source region and the second drain/source region, wherein the first drain/source region, the second drain/source region and the channel form a cloak-shaped active region, wherein the cloak-shaped active region has a V-shaped bottom and wherein a first triangular region of the cloak-shaped active region is embedded in a first isolation region and a second triangular region of the cloak-shaped active region is embedded in a second isolation region; and

a gate electrode wrapping the channel.

9. The device of claim 8, wherein the V-shaped bottom has an interior angle in a range from about 100 degrees to about 110 degrees.

10. The device of claim 8, further comprising:

a first isolation region formed in the substrate;

a second isolation region formed in the substrate, wherein the first isolation region and the second isolation region are formed on opposite sides of the cloak-shaped active region; and

a gate dielectric layer formed between the gate electrode and the cloak-shaped active region.

11. The device of claim 10, wherein the gate dielectric layer comprises:

a first portion formed between the first isolation region and the gate electrode;

a second portion formed between a first sidewall of the cloak-shaped active region and the gate electrode;

a third portion formed between a top surface of the cloak-shaped active region and the gate electrode;

a fourth portion formed between a second sidewall of the cloak-shaped active region and the gate electrode; and

a fifth portion formed between the second isolation region and the gate electrode.

12. The device of claim 10, wherein:

the first isolation region comprises a shallow trench isolation structure; and

the second isolation region comprises the shallow trench isolation structure.

13. The device of claim 8, wherein:

the first drain/source region is formed of silicon germanium;

the second drain/source region is formed of silicon germanium; and

the channel is formed of silicon germanium.