Charge compensation semiconductor device

• US 8,742,550 B2
• Filed: 07/05/2012
• Issued: 06/03/2014
• Est. Priority Date: 07/05/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans, Hirler, Franz
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US13/541,884
• Publication Number:
  US 20140008717A1
• Time in Patent Office: 698 Days
• Field of Search: 257/655, 257/330
• US Class Current: 257/655
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A semiconductor device is provided. The semiconductor device includes a semiconductor body and a source metallization which is arranged on the semiconductor body. The semiconductor body includes in a cross-section a drift region of a first conductivity type, a first body region of a second conductivity type which adjoins the drift region, a first compensation region of the second conductivity type which adjoins the first body region, has a lower maximum doping concentration than the first body region and forms a first pn-junction with the drift region, and a first charge trap. The first charge trap adjoins the first compensation region and includes a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate. The source metallization is arranged in resistive electric connection with the first body region. Further, a method for producing a semiconductor device is provided.

Claims

1. A semiconductor device, comprising:

a semiconductor body comprising in a first cross-section;

a drift region of a first conductivity type;

a first body region of a second conductivity type which adjoins the drift region;

a first compensation region of the second conductivity type which adjoins the first body region, has a lower maximum doping concentration than the first body region and forms a first pn-junction with the drift region; and

a first charge trap adjoining the first compensation region and comprising a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate; and

a source metallization arranged on the semiconductor body and in resistive electric connection with the first body region.

2. The semiconductor device of claim 1, further comprising in the first cross-section:

a second body region of the second conductivity type which is spaced apart from the first body region and in resistive electric connection with the first body region;

a second compensation region of the second conductivity type which adjoins the second body region, has a lower maximum doping concentration than the second body region, forms a second pn-junction with the drift region and is in resistive electric connection with the source metallization; and

a second charge trap adjoining the second compensation region and comprising a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate.

3. The semiconductor device of claim 2, wherein the first charge trap adjoins the second compensation region.

4. The semiconductor device of claim 2, wherein the semiconductor body comprises a first surface having a normal direction defining a vertical direction, wherein the source metallization is arranged on the first surface, and wherein the cross-section is a vertical cross-section, the semiconductor device further comprising a drain metallization arranged opposite to the source metallization and in resistive electric connection with the drift region, wherein the field plate has a minimum distance to the first surface, and wherein a space charge region extends in the drift region between the first compensation region and the second compensation region and vertically below the minimum distance when a reverse voltage is applied between the source metallization and the drain metallization which is higher than a threshold voltage, and wherein the threshold voltage is not larger than about a quarter of a rated blocking voltage of the semiconductor device.

5. The semiconductor device of claim 1, wherein the field plate comprises, in the first cross-section, a first portion which adjoins the first compensation region and a second portion which is spaced apart from the first portion.

6. The semiconductor device of claim 1, wherein the field plate is in resistive electric connection with the source metallization.

7. The semiconductor device of claim 1, wherein the field plate comprises at least one charge generating center.

8. The semiconductor device of claim 1, wherein the field plate comprises at least one of a cavity, a polycrystalline semiconductor material, an amorphous semiconductor material, a semiconductor material comprising lattice defects, a semiconductor material with impurities forming deep traps, a p-doped silicon, a silicide and a metal.

9. The semiconductor device of claim 1, wherein the insulating region adjoins the first pn-junction.

10. The semiconductor device of claim 1, wherein the insulating region is, in the first cross-section, substantially U-shaped or V-shaped.

11. The semiconductor device of claim 1, wherein the insulating region comprises, in the first cross-section, a first portion which is arranged between the field plate and the first compensation region and adjoins the field plate at least at a top side of the field plate, and a second portion which is spaced apart from the first portion and adjoins at least a bottom side of the field plate, the bottom side being arranged opposite to the top side.

12. The semiconductor device of claim 11, wherein at least one of the first portion and the second portion is substantially U-shaped or V-shaped.

13. The semiconductor device of claim 1, wherein the drift region comprises a first portion of the first conductivity type having a first maximum doping concentration and adjoining the first body region, and a second portion of the first conductivity type which adjoins the first portion of the drift region and the first charge trap and comprises a second doping concentration which is higher than the first doping concentration.

14. The semiconductor device of claim 1, wherein the semiconductor body comprises a first surface having a normal direction defining a vertical direction, wherein the source metallization is arranged on the first surface, and wherein the first charge trap is, in the first cross-section, arranged substantially below the first compensation region.

15. The semiconductor device of claim 2, further comprising a third charge trap which is, in the first cross-section, arranged between the first charge trap and the second charge trap, and comprises a field plate and an insulating region which adjoins the drift region and partly surrounds the field plate.

16. The semiconductor device of claim 15, wherein the first compensation region and the second compensation region are, in a second cross-section which is substantially orthogonal to the first cross-section, shaped as substantially parallel bars, and wherein the field plates of the first, second and third charge traps are, in the second cross-section, shaped as bars which are substantially parallel to each other and tilted with respect to the first compensation region and the second compensation region.

17. The semiconductor device of claim 1, further comprising:

a drain region of the first conductivity type comprising a maximum doping concentration which is higher than a maximum doping concentration of the drift region; and

a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and comprising at least one of a floating field plate and a floating charge trap.

18. The semiconductor device of claim 1, wherein the first compensation region is, in the first cross-section, formed as one of a pillar which is substantially orientated in a normal direction of the first cross-section and a strip-type parallelepiped which is substantially orientated in the normal direction.

19. A semiconductor device, comprising:

a semiconductor body having a first surface and comprising a drift region of a first conductivity type, a plurality of compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and adjoins a respective body region of the second conductivity type which has a higher maximum doping concentration than the adjoining compensation region, and a plurality of charge traps each of which comprises a field plate and a insulating region which partly surrounds the field plate, wherein each of the plurality of charge traps adjoins at least one of the plurality of compensation regions; and

a source metallization arranged on the first surface and in resistive electric connection with each of the compensation regions.

20. The semiconductor device of claim 19, wherein the plurality of compensation regions forms a first lattice when seen in a normal direction of the first surface, and wherein the plurality of charge traps forms a second lattice when seen in the normal direction.

21. The semiconductor device of claim 20, wherein a lattice constant of the second lattice is smaller than a lattice constant of the first lattice.

22. The semiconductor device of claim 20, wherein the second lattice is tilted with respect to the first lattice.

23. A method for producing a semiconductor device, comprising:

providing a semiconductor body having a main surface with a normal direction and comprising a semiconductor layer of a first conductivity type extending to the main surface;

forming in the semiconductor body a plurality of charge trap structures each of which comprises a field plate which is, in a cross-section which is substantially orthogonal to the main surface, partly surrounded by an insulating region;

forming a plurality of compensation regions of a second conductivity type so that each compensation region forms a respective pn-junction within the semiconductor body and that each compensation region adjoins, in the cross-section, at least one of the charge trap structures; and

forming a source metallization in resistive electric connection with each of the plurality of compensation regions.

24. The method of claim 23, wherein forming the charge trap structures comprises at least one of:

etching trenches from the main surface into the semiconductor body;

etching trenches into the semiconductor body from a surface of the semiconductor body which is substantially orthogonal to the main surface;

insulating side walls and bottom walls of the trenches;

at least partly filling each of the trenches with a conductive region; and

forming charge generating centers in at least one of the conductive regions.

25. The method of claim 23, wherein forming the plurality of compensation regions comprises at least one of:

forming at least one epitaxial layer of the first conductivity type on the semiconductor layer using epitaxial deposition;

masked implanting of dopants of the second conductivity type in the at least one epitaxial layer;

etching additional trenches into at least one of the semiconductor body and the at least one epitaxial layer; and

filling the additional trenches with a semiconductor material of the second conductivity type.