Solder interconnect on IC chip

• US 8,742,582 B2
• Filed: 10/11/2011
• Issued: 06/03/2014
• Est. Priority Date: 09/20/2004
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megit Acquisition Corp.
• Inventors: Lin, Mou-Shiung
• Primary Examiner(s): Fahmy, Wael
• Assistant Examiner(s): SALERNO, SARAH KATE
• Application Number:
  US13/271,004
• Publication Number:
  US 20120025378A1
• Time in Patent Office: 966 Days
• Field of Search: 257/758, 257/E23.017, 257/E23.018, 257/E23.019, 257/E23.129
• US Class Current: 257/758
• CPC Class Codes: H01L 2224/0554 External layer
• CPC Class Codes: H01L 2224/0555 Shape
• CPC Class Codes: H01L 2224/0556 Disposition
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/06167 with specially adapted redistribution layers [RDL]
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/16106 the bump connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides

Abstract

A semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump. The bump is connected to the line and is adapted to be electrically connected to the line. A plane that is horizontal to an active surface of the semiconductor chip is defined. The area that the connection region of the line and the bump is projected on the plane is larger than 30,000 square microns or has an extension distance larger than 500 microns.

Claims

1. A chip package comprising:

a semiconductor chip comprising a semiconductor substrate, a first conductive structure coupled to said semiconductor substrate, wherein said first conductive structure comprises a first conductive layer and a second conductive layer coupled to said first conductive layer, a dielectric layer between said first and second conductive layers, a separating layer coupled tosaid semiconductor substrate, said first conductive structure and said dielectric layer, wherein an opening in said separating layer exposes a contact point of said first conductive structure, and said contact point is within said opening, and a second conductive structure on said contact point, wherein said second conductive structure is coupled to said contact point through said opening, wherein said second conductive structure comprises a first copper layer;

a circuit substrate;

a conductive interconnect between said second conductive structure and a conductive contact of said circuit substrate and coupled to said contact point, wherein said second conductive structure is coupled to said conductive contact through said conductive interconnect, wherein said conductive interconnect comprises tin, wherein from a first perspective view said conductive interconnect extends a distance greater than a width of said conductive interconnect, wherein a first contact area between said conductive contact and said conductive interconnect is greater than 30,000 square micrometers; and

a first polymer layer and a second polymer layer between said semiconductor chip and said circuit substrate, wherein said first polymer layer contacts said semiconductor chip, said conductive structure, and a sidewall of said conductive interconnect, wherein said second polymer layer is directly coupled to said circuit substrate, directly on said first polymer layer, and directly coupled to said conductive interconnect at a sidewall of said conductive interconnect.

2. The chip package of claim 1, wherein said first contact area has an extending distance greater than 500 micrometers.

3. The chip package of claim 1, wherein said second conductive structure further comprises a titanium-containing layer coupled to said first copper layer.

4. The chip package of claim 1, wherein said conductive interconnect comprises a tin-silver alloy.

5. The chip package of claim 1, wherein said separating layer comprises a nitride.

6. The chip package of claim 1, wherein said first contact area is greater than 80,000 square micrometers.

7. The chip package of claim 1, wherein said first contact area is greater than 150,000 square micrometers.

8. The chip package of claim 1, wherein said first copper layer has a thickness greater than 3 micrometers.

9. The chip package of claim 1, wherein said second conductive layer comprises a second copper layer.

10. The chip package of claim 1, wherein a second contact area between said contact point and said second conductive structure is greater than 30,000 square micrometers.

11. The chip package of claim 10, wherein said second contact area is greater than 80,000 square micrometers.

12. The chip package of claim 1, wherein said second conductive structure further comprises a nickel layer on said first copper layer.

13. The chip package of claim 1, wherein from said first perspective view a second contact area between said contact point and said second conductive structure extends a distance greater than 500 micrometers.

14. The chip package of claim 1, wherein said distance extends in a direction perpendicular to said width.

15. A chip package comprising:

a semiconductor chip comprising a semiconductor substrate, a first conductive structure coupled to said semiconductor substrate, wherein said first conductive structure comprises a first conductive layer and a second conductive layer coupled to said first conductive layer, a dielectric layer between said first and second conductive layers, a separating layer coupled to said semiconductor substrate, said first conductive structure and said dielectric layer, wherein an opening in said separating layer exposes a contact point of said first conductive structure, and said contact point is within said opening, and a second conductive structure on said contact point, wherein said second conductive structure is coupled to said contact point through said opening, wherein said second conductive structure comprises a first copper layer;

a circuit substrate;

a conductive interconnect between said second conductive structure and a conductive contact of said circuit substrate and coupled to said contact point, wherein said second conductive structure is coupled to said conductive contact through said conductive interconnect wherein said conductive interconnect comprises tin, wherein from a first perspective view said conductive interconnect extends a distance greater than a width of said conductive interconnect, wherein a first contact area between said conductive contact and said conductive interconnect has an extending distance greater than 500 micrometers; and

a first polymer layer and a second polymer layer between said semiconductor chip and said circuit substrate, wherein said first polymer layer contacts said semiconductor chip, said conductive structure, and a sidewall of said conductive interconnect, wherein said second polymer layer is directly coupled to said circuit substrate, directly on said first polymer layer, and directly coupled to said conductive interconnect at a sidewall of said conductive interconnect.

16. The chip package of claim 15, wherein said second conductive structure further comprises a titanium-containing layer coupled to said first copper layer.

17. The chip package of claim 15, wherein said conductive interconnect comprises a tin-silver alloy.

18. The chip package of claim 15, wherein said separating layer comprises a nitride.

19. The chip package of claim 15, wherein said extending distance is greater than 800 micrometers.

20. The chip package of claim 15, wherein said extending distance is greater than 1200 micrometers.

21. The chip package of claim 15, wherein said first copper layer has a thickness greater than 3 micrometers.

22. The chip package of claim 15, wherein said conductive layer comprises a second copper layer.

23. The chip package of claim 15, wherein a second contact area between said contact point and said second conductive structure is greater than 30,000 square micrometers.

24. The chip package of claim 23, wherein said second contact area is greater than 80,000 square micrometers.

25. The chip package of claim 15, wherein said second conductive structure further comprises a nickel layer on said first copper layer.

26. The chip package of claim 15, wherein from said first perspective view a second contact area between said contact point and said second conductive structure extends a distance greater than 500 micrometers.

27. The chip package of claim 15, wherein said distance extends in a direction perpendicular to said width.

28. A chip package comprising:

a semiconductor chip comprising a semiconductor substrate, a first conductive structure coupled to said semiconductor substrate, wherein said first conductive structure comprises a first conductive layer and a second conductive layer coupled to said first conductive layer, a dielectric layer between said first and second conductive layers, a passivation layer coupled to said semiconductor substrate, said first conductive and said dielectric layer, wherein said passivation layer comprises a nitride, wherein an opening in said passivation layer exposes a contact point of said first conductive structure, and said contact point is within said opening, and a second conductive structure on said contact point, wherein said second conductive structure is coupled to said contact point through said opening, wherein said second conductive structure comprises a first copper layer having a thickness greater than 3 micrometers;

a circuit substrate;

a conductive interconnect between said second conductive structure and a conductive contact of said circuit substrate and coupled to said contact point, wherein said second conductive structure is coupled to said conductive contact through said conductive interconnect wherein said conductive interconnect comprises tin, wherein from a first perspective view said conductive interconnect extends a distance greater than a width of said conductive interconnect; and

a first polymer layer and a second polymer layer between said semiconductor chip and said circuit substrate, wherein said first polymer layer contacts said semiconductor chip, said conductive structure, and a sidewall of said conductive interconnect, wherein said second polymer layer is directly coupled to said circuit substrate, directly on said first polymer layer, and directly coupled to said conductive interconnect at a sidewall of said conductive interconnect.

29. The chip package of claim 28, wherein said second conductive structure further comprises a titanium-containing layer coupled to said first copper layer.

30. The chip package of claim 28, wherein said conductive interconnect comprises a tin-silver alloy.

31. The chip package of claim 28, wherein a contact area between said conductive contact and said conductive interconnect has an extending distance greater than 500 micrometers.

32. The chip package of claim 28, wherein a contact area between said conductive contact and said conductive interconnect is greater than 30,000 square micrometers.

33. The chip package of claim 28, wherein said second conductive layer comprises a second copper layer.

34. The chip package of claim 28, wherein a contact area between said contact point and said second conductive is greater than 30,000 square micrometers.

35. The chip package of claim 28, wherein said second conductive structure further comprises a nickel layer on said first copper layer.

36. The chip package of claim 28, wherein from said first perspective view a contact area between said contact point and said second conductive structure extends a distance greater than 500 micrometers.

37. The chip package of claim 28, wherein said distance extends in a direction perpendicular to said width.