Seal ring in an integrated circuit die

• US 8,742,583 B2
• Filed: 01/16/2012
• Issued: 06/03/2014
• Est. Priority Date: 01/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chuan-Yi, Hao, Ching-Chen, Chou, Chen Cheng, Lin, Sheng-Yuan
• Primary Examiner(s): Clark, S. V.
• Application Number:
  US13/351,144
• Publication Number:
  US 20120112322A1
• Time in Patent Office: 869 Days
• Field of Search: 257/758, 257/750, 257/784, 257/786, 257/774
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05116 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05609 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05616 Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 : of an individual bump connector
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06527 : Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/585 : comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

The formation of a seal ring in a semiconductor integrated circuit (IC) die is described. Through-silicon vias (TSVs) are typically formed in a semiconductor IC die to facilitate the formation of a three dimensional (3D) stacking die structure. The TSVs may be utilized to provide electrical connections between components in different dies of the 3D stacking die structure. A seal ring is formed in the inter-metal dielectric (IMD) layers of an IC die, enclosing an active circuit region. The real ring is formed prior to the formation of the TSVs, preventing moistures or other undesired chemical agents from diffusing into the active circuit region during the subsequent processes of forming TSVs.

Claims

1. A device comprising:

a first die having a substrate, the substrate having formed thereon an active circuit region having one or more semiconductor devices;

a plurality of metal interconnect layers formed over the substrate, including a top metal interconnect layer;

a through via extending from the top metal interconnect layer through the substrate; and

a seal ring interposed between the active region and the through via, the seal ring comprising a plurality of stacked features formed in respective ones of the plurality of metal interconnect layers.

2. The device of claim 1 further comprising at least one additional metal layer above the top metal interconnect layer.

3. The device of claim 1 wherein the seal ring is substantially aligned with a periphery of the active circuit region.

4. The device of claim 1 further comprising:

a dielectric layer over the top metal layer; and

a bonding contact on the dielectric layer, wherein the bonding contact is coupled to the through via and to at least one of the semiconductor devices through a redistribution feature in a first insulating layer between the dielectric layer and the top metal interconnect layer.

5. The device of claim 4 further comprising:

a second die, the first die being coupled to the second die through the bonding contact on the first substrate and a corresponding bonding contact on the second die.

6. The device of claim 5 further comprising:

a second dielectric layer over a back-side surface of the first die; and

a second bonding contact on the second dielectric layer, wherein the second bonding contact is coupled the through via through a second redistribution features in a second insulating layer between the second dielectric layer and the back-side surface of the first die.

7. The device of claim 1 wherein the seal ring further comprises:

a metal feature in each of the plurality of metal interconnect layers; and

a via feature electrically connecting each metal feature in each of the plurality of metal interconnect layers, each via feature comprising two vias.

8. The device of claim 1 wherein the seal ring comprises a continuous unbroken feature extending around the periphery of the active region.

9. The device of claim 1 wherein the seal ring comprises a plurality of non-contiguous features extending around the periphery of the active region.

10. An integrated circuit comprising:

a substrate, the substrate having an active region, a seal ring region substantially surrounding a periphery of the active region, and a TSV region, the TSV region being at an opposed side of the seal ring region relative the active region;

a functional circuit within the active region;

a seal ring in the seal ring region, the seal ring including a stack of metal features and via features extending from a first metal interconnect layer to a top metal interconnect layer;

a via in the TSV region, the via extending through the substrate; and

a first electrical contact at a top of the via and a second electrical contact at a bottom of the via.

11. The integrated circuit of claim 10 wherein the seal ring further comprises a stack of alternating metal interconnect features and via features.

12. The integrated circuit of claim 11 wherein the via features each comprise two or more via rings.

13. The integrated circuit of claim 10 wherein the via in the TSV region is a through-silicon via.

14. The integrated circuit of claim 10 further comprising a redistribution layer electrically coupling the via in the TSV region to the functional circuit in the active region.

15. The integrated circuit of claim 10 wherein the electrical contact at the bottom of the via includes a solder ball.

16. A package comprising:

a first device including;

a substrate, the substrate including an active region, a through via region, and a seal ring region, the seal ring region substantially surrounding the active region and interposed between the active region and the through via region;

a seal ring within the seal ring region, the seal ring comprising a stack of metal interconnect features alternating with via features, the seal ring extending about a periphery of the active region;

a through via in the through via region, the through via extending from a top to a bottom of the substrate;

a second device;

an interconnect structure electrically coupling a top of the through via and the second device;

a package substrate; and

a second interconnect structure electrically coupling a bottom of the through via to the package substrate.

17. The package of claim 16 wherein the interconnect structure includes a first contact pad coupled to a second contact pad.

18. The package of claim 16 wherein the second interconnect structure includes a solder ball.

19. The package of claim 16 wherein the package substrate is a printed circuit board.

20. The package of claim 16 wherein the first device is selected from the group consisting of an integrated circuit and a wafer.