Divider circuit and semiconductor device using the same
First Claim
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1. A divider circuit comprising:
- a flip-flop circuit including;
a first input portion configured to be supplied with a clock signal;
a first output portion configured to supply a first output signal;
a second output portion configured to supply an inversion signal of the first output signal;
a second input portion electrically connected to the second output portion;
a first transistor comprising a source and a drain, wherein one of the source and the drain is electrically connected to the second input portion, and wherein a gate of the first transistor is configured to be supplied with an inversion signal of the clock signal;
a second transistor having a gate electrically connected to the other of the source and the drain of the first transistor;
a third transistor having a gate electrically connected to the first input portion;
a fourth transistor having a gate electrically connected to one of a source and a drain of the third transistor,wherein a channel formation region of the first transistor comprises an oxide semiconductor including indium, andwherein a channel formation region of the third transistor comprises an oxide semiconductor including indium.
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Abstract
A semiconductor device with low power consumption and a small area is provided. By using a transistor including an oxide semiconductor for a channel as a transistor included in a flip-flop circuit, a divider circuit in which the number of transistors is small, power consumption is low, and the area is small can be achieved. By using the divider circuit, a semiconductor device which operates stably and is highly reliable can be provided.
109 Citations
19 Claims
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1. A divider circuit comprising:
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a flip-flop circuit including; a first input portion configured to be supplied with a clock signal; a first output portion configured to supply a first output signal; a second output portion configured to supply an inversion signal of the first output signal; a second input portion electrically connected to the second output portion; a first transistor comprising a source and a drain, wherein one of the source and the drain is electrically connected to the second input portion, and wherein a gate of the first transistor is configured to be supplied with an inversion signal of the clock signal; a second transistor having a gate electrically connected to the other of the source and the drain of the first transistor; a third transistor having a gate electrically connected to the first input portion; a fourth transistor having a gate electrically connected to one of a source and a drain of the third transistor, wherein a channel formation region of the first transistor comprises an oxide semiconductor including indium, and wherein a channel formation region of the third transistor comprises an oxide semiconductor including indium.
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2. A divider circuit according to claim 1,
wherein a channel formation region of the second transistor comprises an oxide semiconductor, and wherein a channel formation region of the fourth transistor comprises an oxide semiconductor.
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3. A semiconductor device comprising the divider circuit according to claim 1.
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4. A divider circuit comprising:
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a first inverter and a second inverter; a first transistor and a fifth transistor which are p-channel transistors; and a second transistor, a third transistor, a fourth transistor, a sixth transistor, a seventh transistor, and an eighth transistor which are n-channel transistors, wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a first power supply, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the seventh transistor are electrically connected to a second power supply, wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a gate of the eighth transistor and an input of the first inverter, wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the seventh transistor, wherein an input of the second inverter is electrically connected to the other of the source and the drain of the fifth transistor and the one of the source and the drain of the sixth transistor, wherein an output of the second inverter is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the third transistor, and wherein an output of the first inverter is electrically connected to a gate of the fourth transistor, a gate of the fifth transistor, and a gate of the sixth transistor.
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5. The divider circuit according to claim 4, wherein the first power supply supplies a higher potential than the second power supply.
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6. The divider circuit according to claim 4, wherein a capacitor is electrically connected to at least one of the input of the second inverter and the one of the source and the drain of the eighth transistor.
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7. The divider circuit according to claim 4, wherein a channel formation region of the fourth transistor comprises an oxide semiconductor.
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8. The divider circuit according to claim 4, wherein a channel formation region of the eighth transistor comprises an oxide semiconductor.
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9. The divider circuit according to claim 4, wherein a channel formation region of at least one of the second transistor and the third transistor comprises an oxide semiconductor.
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10. The divider circuit according to claim 4, wherein a channel formation region of at least one of the sixth transistor and the seventh transistor comprises an oxide semiconductor.
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11. A semiconductor device comprising the divider circuit according to claim 4.
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12. A divider circuit comprising:
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a first inverter; a first transistor and a fifth transistor which are p-channel transistors; and a second transistor, a third transistor, a fourth transistor, a sixth transistor, a seventh transistor, and an eighth transistor which are n-channel transistors, wherein one of a source and a drain of the first transistor and one of a source and a drain of the fifth transistor are electrically connected to a first power supply, wherein the other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor, wherein the other of the source and the drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor, wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor, wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the seventh transistor are electrically connected to a second power supply, wherein a gate of the first transistor and a gate of the second transistor are electrically connected to a gate of the eighth transistor, wherein one of a source and a drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor and the one of the source and the drain of the second transistor, wherein the other of the source and the drain of the eighth transistor is electrically connected to a gate of the seventh transistor, wherein an input of the first inverter is electrically connected to the other of the source and the drain of the fifth transistor and the one of the source and the drain of the sixth transistor, wherein an output of the first inverter is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the fourth transistor is electrically connected to a gate of the third transistor, and wherein a gate of the fourth transistor is electrically connected to a gate of the fifth transistor, and a gate of the sixth transistor.
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13. The divider circuit according to claim 12, wherein the first power supply supplies a higher potential than the second power supply.
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14. The divider circuit according to claim 12, wherein a capacitor is electrically connected to at least one of the input of the first inverter and the one of the source and the drain of the eighth transistor.
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15. The divider circuit according to claim 12, wherein a channel formation region of the fourth transistor comprises an oxide semiconductor.
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16. The divider circuit according to claim 12, wherein a channel formation region of the eighth transistor comprises an oxide semiconductor.
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17. The divider circuit according to claim 12, wherein a channel formation region of at least one of the second transistor and the third transistor comprises an oxide semiconductor.
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18. The divider circuit according to claim 12, wherein a channel formation region of at least one of the sixth transistor and the seventh transistor comprises an oxide semiconductor.
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19. A semiconductor device comprising the divider circuit according to claim 12.
Specification