Display device
First Claim
1. A semiconductor device comprising:
- a pixel portion formed over a substrate;
a scan line driver circuit formed over the substrate, the scan line driver circuit comprising;
a shift register comprising;
an output terminal;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor; and
an eighth transistor;
a first switch formed over the substrate; and
a second switch formed over the substrate,wherein one of a source and a drain of the first transistor is directly connected to the output terminal,wherein one of a source and a drain of the second transistor is directly connected to the output terminal,wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor,wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor,wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor,wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor,wherein a gate of the eighth transistor is directly connected to the gate of the first transistor,wherein a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor,wherein a clock signal is input to a gate of the third transistor,wherein the output terminal is operationally connected to a scan line,wherein a wiring is electrically connected to a first signal line via the first switch,wherein the wiring is electrically connected to a second signal line via the second switch,wherein the wiring is electrically connectable to a driver IC, andwherein the second transistor comprises a channel region comprising an oxide semiconductor.
1 Assignment
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Accused Products
Abstract
To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.
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Citations
15 Claims
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1. A semiconductor device comprising:
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a pixel portion formed over a substrate; a scan line driver circuit formed over the substrate, the scan line driver circuit comprising; a shift register comprising; an output terminal; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor; a first switch formed over the substrate; and a second switch formed over the substrate, wherein one of a source and a drain of the first transistor is directly connected to the output terminal, wherein one of a source and a drain of the second transistor is directly connected to the output terminal, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor, wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor, wherein a gate of the eighth transistor is directly connected to the gate of the first transistor, wherein a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a clock signal is input to a gate of the third transistor, wherein the output terminal is operationally connected to a scan line, wherein a wiring is electrically connected to a first signal line via the first switch, wherein the wiring is electrically connected to a second signal line via the second switch, wherein the wiring is electrically connectable to a driver IC, and wherein the second transistor comprises a channel region comprising an oxide semiconductor. - View Dependent Claims (2, 3, 4, 5)
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6. A semiconductor device comprising:
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a pixel portion formed over a substrate; a scan line driver circuit formed over the substrate, the scan line driver circuit comprising; a shift register comprising; an output terminal; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor; and a signal line driver circuit comprising; a first switch formed over the substrate; a second switch formed over the substrate; and a driver IC formed by utilizing a single crystalline substrate, wherein one of a source and a drain of the first transistor is directly connected to the output terminal, wherein one of a source and a drain of the second transistor is directly connected to the output terminal, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor, wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor, wherein a gate of the eighth transistor is directly connected to the gate of the first transistor, wherein a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a clock signal is input to a gate of the third transistor, wherein the output terminal is operationally connected to a scan line, wherein a wiring is electrically connected to a first signal line via the first switch, wherein the wiring is electrically connected to a second signal line via the second switch, wherein the wiring is electrically connected to the driver IC, and wherein the second transistor comprises a channel region comprising an oxide semiconductor. - View Dependent Claims (7, 8, 9, 10)
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11. A semiconductor device comprising:
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a pixel portion formed over a substrate; and a scan line driver circuit formed over the substrate, the scan line driver circuit comprising; a shift register comprising; an output terminal; a first transistor; a second transistor; a third transistor; a fourth transistor; a fifth transistor; a sixth transistor; a seventh transistor; and an eighth transistor, wherein one of a source and a drain of the first transistor is directly connected to the output terminal, wherein one of a source and a drain of the second transistor is directly connected to the output terminal, wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor, wherein a gate of the fourth transistor is directly connected to a gate of the second transistor, wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor, wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor, wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor, wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor, wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor, wherein a gate of the eighth transistor is directly connected to the gate of the first transistor, wherein a gate of the fifth transistor is directly connected to the other of the source and the drain of the fifth transistor, wherein a clock signal is input to a gate of the third transistor, and wherein the second transistor comprises a channel region comprising an oxide semiconductor. - View Dependent Claims (12, 13, 14, 15)
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Specification