Display device

• US 8,743,307 B2
• Filed: 06/07/2012
• Issued: 06/03/2014
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Klaus Schmidt, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Kobe Steel Limited, Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Jae Woo, Lee, Je Hun, Ahn, Byung Du, Park, Sei-Yong, Park, Jun Hyun, Lim, Ji Hun, Lee, Kyoung Won, Kugimiya, Toshihiro, Miki, Aya, Morita, Shinya, Goto, Hiroshi, Kim, Gun Hee, Kishi, Tomoya, Tao, Hiroaki
• Primary Examiner(s): Vu, Phu
• Application Number:
  US13/490,978
• Publication Number:
  US 20130114013A1
• Time in Patent Office: 726 Days
• Field of Search: 349/43
• US Class Current: 349/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

A display device includes a first substrate, a gate line disposed on the first substrate and including a gate electrode, a gate insulating layer disposed on the gate line, a semiconductor layer disposed on the gate insulating layer, a data line disposed on the semiconductor layer and connected to a source electrode, a drain electrode disposed on the semiconductor layer and facing the source electrode and a passivation layer disposed on the data line, in which the semiconductor layer is formed of an oxide semiconductor including indium, tin, and zinc. The indium is present in an amount of about 5 atomic percent (at %) to about 50 at %, and a ratio of the zinc to the tin is about 1.38 to about 3.88.

Claims

1. A display device, comprising:

a first substrate;

a gate line disposed on the first substrate and comprising a gate electrode;

a semiconductor layer disposed on the first substrate;

a gate insulating layer disposed between the gate electrode and the semiconductor layer;

a data line disposed on the first substrate and connected to a source electrode; and

a drain electrode facing the source electrode,

wherein the semiconductor layer comprises an oxide semiconductor including indium, tin, and zinc, wherein the indium is present in an amount of about 5 atomic percent (at %) to about 50 at %, and wherein a ratio of the zinc to the tin is about 1.38 to about 3.88.

2. The display device of claim 1, wherein:

the indium is present in an amount of about 10 at % to about 30 at % and

the ratio of the zinc to the tin is about 1.78 to about 2.95.

3. The display device of claim 2, wherein:

an etch rate of the semiconductor layer is about 10 Å

/second to about 200 Å

/second.

4. The display device of claim 3, wherein:

the semiconductor layer has a same planar pattern as the source electrode, the drain electrode, and the data line except for a channel portion formed in the semiconductor layer.

5. The display device of claim 4, wherein:

a threshold voltage Vth of the semiconductor layer is more than about −

10V.

6. The display device of claim 5, wherein:

a charge mobility of the semiconductor layer is about 5 cm2/Vs.

7. The display device of claim 6, wherein:

the gate insulating layer comprises a lower layer and an upper layer.

8. The display device of claim 7, wherein:

the lower layer comprises silicon oxide.

9. The display device of claim 8, wherein:

the upper layer comprises silicon nitride.

10. The display device of claim 9, further comprising:

a passivation layer disposed on the data line and

a pixel electrode disposed on the passivation layer,

wherein the passivation layer has a contact hole and the pixel electrode is connected to the drain electrode through the contact hole.

11. The display device of claim 10, further comprising:

a second substrate facing the first substrate,

wherein a liquid crystal layer is interposed between the first substrate and the second substrate.

12. The display device of claim 1, wherein:

an etch rate of the semiconductor layer is about 10 Å

/second to about 200 Å

/second.

13. The display device of claim 12, wherein:

the semiconductor layer has a same planar pattern as the source electrode, the drain electrode, and the data line except for a channel portion formed in the semiconductor layer.

14. The display device of claim 13, wherein:

the gate insulating layer comprises a lower layer and an upper layer.

15. The display device of claim 14, wherein:

the lower layer comprises silicon oxide and the upper layer comprises silicon nitride.

16. The display device of claim 15, further comprising:

a passivation layer disposed on the data line and

a pixel electrode disposed on the passivation layer,

wherein the passivation layer has a contact hole and the pixel electrode is connected to the drain electrode through the contact hole.

17. The display device of claim 1, wherein:

the indium is present in an amount of about 10 at % and

the ratio of the zinc to the tin is about 1.78 to about 3.88.

18. The display device of claim 1, wherein:

the indium is present in an amount of about 20 at % and

the ratio of the zinc to the tin is about 1.50 to about 3.23.

19. The display device of claim 1, wherein:

the indium is present in an amount of about 30 at % and

the ratio of the zinc to the tin is about 1.38 to about 2.95.

20. A display device, comprising:

a first substrate;

a gate line disposed on the first substrate and including a gate electrode;

a semiconductor layer disposed on the first substrate;

a gate insulating layer disposed between the gate electrode and the semiconductor layer;

a data line disposed on the first substrate and connected to a source electrode; and

a drain electrode facing the source electrode,

wherein the semiconductor layer comprises an oxide semiconductor including indium, tin, and zinc,

wherein the indium is present in an amount of about 5 atomic percent (at %) to about 50 at %,

wherein the zinc is present in an amount of about 25 at % to about 71.6 at %, and

wherein the tin is present in an amount of about 16.1 at % to about 33.3 at %.