Memory device and semiconductor device using the same

• US 8,743,590 B2
• Filed: 04/05/2012
• Issued: 06/03/2014
• Est. Priority Date: 04/08/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): DINH, SON T
• Application Number:
  US13/440,093
• Publication Number:
  US 20120257439A1
• Time in Patent Office: 789 Days
• Field of Search: 365/149, 365/203, 365/189.05
• US Class Current: 365/149
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 29/50016 of retention

Abstract

A memory device whose speed at the time of operation such as writing or reading is high and whose number of semiconductor elements per memory cell is small is provided. The memory device includes a control unit, an arithmetic unit, and a buffer memory device. The buffer memory device stores data sent from a main memory device and/or the arithmetic unit, in accordance with an instruction from the control unit. The buffer memory device includes a plurality of memory cells. The memory cells each include a transistor including a channel formation region including an oxide semiconductor, and a memory element to which charge with an amount in accordance with a value of the data is supplied through the transistor. Further, a data retention time of the memory cell corresponding to a valid bit is shorter than a data retention time of the memory cell corresponding to a data field.

Claims

1. A memory device comprising:

a first memory cell and a second memory cell each comprising;

a first transistor; and

a memory element to which charge with an amount in accordance with data is supplied through the first transistor,

wherein the first memory cell corresponds to a valid bit,

wherein the second memory cell corresponds to a data field, and

wherein a retention time of the first memory cell is shorter than a retention time of the second memory cell.

2. A memory device according to claim 1,

wherein the first transistor comprises an oxide semiconductor.

3. A memory device according to claim 1,

wherein a capacitance value of the first memory cell is smaller than a capacitance value of the second memory cell.

4. A memory device according to claim 1, further comprising:

a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through respective data lines, the first logic circuit and the second logic circuit each including a logic element,

wherein the charge with the amount in accordance with the data is supplied from the data line through the first transistor to the memory element, and

wherein a threshold potential of the first logic circuit is higher than a threshold potential of the second logic circuit.

5. A memory device according to claim 1,

a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through respective data lines, the first logic circuit and the second logic circuit each including a logic element;

and

a first capacitor and a second capacitor connected to the first memory cell and the second memory cell through the respective data lines,

wherein a capacitance value of the first capacitor is smaller than a capacitance value of the second capacitor.

6. A memory device according to claim 1, further comprising:

a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through respective data lines, the first logic circuit and the second logic circuit each including a logic element,

wherein the first memory cell and the second memory cell each comprises a capacitor to which the charge with the amount in accordance with the data supplied from the data line through the first transistor, and

wherein a channel width of the first transistor of the first memory cell is larger than a channel width of the first transistor of the second memory cell.

7. A memory device according to claim 1, further comprising:

a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through respective data lines, the first logic circuit and the second logic circuit each including a logic element,

wherein the memory element comprises;

a capacitor to which the charge with the amount in accordance with the data is supplied from the data line through the first transistor; and

a second transistor whose drain current is determined in accordance with the amount of the charge, and

wherein a channel width of the second transistor of the first memory cell is larger than a channel width of the second transistor of the second memory cell.

8. A semiconductor device comprising the memory device according to claim 1, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data sent from at least one of a main memory device and the arithmetic unit, in accordance with an instruction from the control unit.

9. A semiconductor device comprising the memory device according to claim 1, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data including an instruction sent from a main memory device, and

wherein the control unit is configured to read out the data from the buffer memory device and control operation of the arithmetic unit and operation of the buffer memory device in accordance with the instruction.

10. A memory device comprising:

a first memory cell and a second memory cell each comprising;

a transistor; and

a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor,

wherein the first memory cell corresponds to a valid bit,

wherein the second memory cell corresponds to a data field,

wherein the charge with the amount in accordance with the data is supplied from a data line through the first transistor to the memory element, and

wherein, in a period in which the first transistors are off, a potential of the data line of the first memory cell is lower than a potential of the data line of the second memory cell.

11. A memory device according to claim 10,

wherein the transistor comprises an oxide semiconductor.

12. A semiconductor device comprising the memory device according to claim 10, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data sent from at least one of a main memory device and the arithmetic unit, in accordance with an instruction from the control unit.

13. A semiconductor device comprising the memory device according to claim 10, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data including an instruction sent from a main memory device, and

wherein the control unit is configured to read out the data from the buffer memory device and control operation of the arithmetic unit and operation of the buffer memory device in accordance with the instruction.

14. A memory device comprising:

a first memory cell and a second memory cell each comprising;

a transistor; and

a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor,

wherein the first memory cell corresponds to a valid bit,

wherein the second memory cell corresponds to a data field,

wherein a precharge potential applied to the data line of the first memory cell before the data is read is higher than a precharge potential applied to the data line of the second memory cell before the data is read, and

wherein a digital value of the data is determined by comparing the precharge potential with a potential of the data line at the time of reading the data.

15. A memory device according to claim 14,

wherein the transistor comprises an oxide semiconductor.

16. A semiconductor device comprising the memory device according to claim 14, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data sent from at least one of a main memory device and the arithmetic unit, in accordance with an instruction from the control unit.

17. A semiconductor device comprising the memory device according to claim 14, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data including an instruction sent from a main memory device, and

wherein the control unit is configured to read out the data from the buffer memory device and control operation of the arithmetic unit and operation of the buffer memory device in accordance with the instruction.

18. A memory device comprising:

a first memory cell and a second memory cell each comprising;

a transistor; and

a memory element to which charge with an amount in accordance with data is supplied from a data line through the transistor; and

a first logic circuit and a second logic circuit connected to the first memory cell and the second memory cell through the respective data lines, the first logic circuit and the second logic circuit each including a logic element,

wherein the first memory cell corresponds to a valid bit,

wherein the second memory cell corresponds to a data field, and

wherein a precharge potential applied to the data line of the first memory cell before the data is read is lower than a precharge potential applied to the data line of the second memory cell before the data is read.

19. A memory device according to claim 18,

wherein the transistor comprises an oxide semiconductor.

20. A semiconductor device comprising the memory device according to claim 18, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data sent from at least one of a main memory device and the arithmetic unit, in accordance with an instruction from the control unit.

21. A semiconductor device comprising the memory device according to claim 18, further comprising:

a control unit;

an arithmetic unit; and

a buffer memory device comprising the first memory cell and the second memory cell,

wherein the buffer memory device is configured to store the data including an instruction sent from a main memory device, and

wherein the control unit is configured to read out the data from the buffer memory device and control operation of the arithmetic unit and operation of the buffer memory device in accordance with the instruction.

22. The semiconductor device according to claim 4,

wherein the logic element is configured to invert a polarity of an input potential and output an inverted potential.

23. The semiconductor device according to claim 5,

wherein the logic element is configured to invert a polarity of an input potential and output an inverted potential.

24. The semiconductor device according to claim 6,

wherein the logic element is configured to invert a polarity of an input potential and output an inverted potential.

25. The semiconductor device according to claim 7,

wherein the logic element is configured to invert a polarity of an input potential and output an inverted potential.

26. The semiconductor device according to claim 18,

wherein the logic element is configured to invert a polarity of an input potential and output an inverted potential.