Method and apparatus for increasing data retention capability of a non-volatile memory

• US 8,743,609 B1
• Filed: 05/06/2013
• Issued: 06/03/2014
• Est. Priority Date: 12/20/2006
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Montierth, Mark D, Briggs, Randall D., Keithley, Douglas Gene
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US13/888,119
• Time in Patent Office: 393 Days
• Field of Search: 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Semi-volatile NAND flash memory systems, apparatuses, and methods for use are described herein. According to various embodiments, a semi-volatile NAND flash memory may be partitioned into various retention regions. Other embodiments may be described and claimed.

Claims

1. A method comprising:

writing data in a first memory block of a non-volatile memory;

subsequent to writing the data in the first memory block, determining that the data written in the first memory block needs to be refreshed; and

based on determining that the data written in the first memory block needs to be refreshed,

(i) if the first memory block has endured at least a threshold number of erase/write cycles, relocating the data from the first memory block to a second memory block of the non-volatile memory, and

(ii) if the first memory block has endured less than the threshold number of erase/write cycles, refreshing the data in the first memory block of the non-volatile memory.

2. The method of claim 1, wherein determining that the data written in the first memory block needs to be refreshed further comprises:

determining a time that has elapsed since the data was last written or last refreshed in the first memory block;

determining a number of erase/write cycles endured by the first memory block; and

based on (i) the time that has elapsed since the data was last written or last refreshed in the first memory block and (ii) the number of erase/write cycles endured by the first memory block, determining that the data written in the first memory block needs to be refreshed.

3. The method of claim 1, wherein determining that the data written in the first memory block needs to be refreshed further comprises:

determining that the data is written in the first memory block, without having been refreshed, for at least a threshold period of time; and

based on determining that the data is written in the first memory block, without having been refreshed, for at least the threshold period of time, determining that the data written in the first memory block needs to be refreshed.

4. The method of claim 3, wherein the threshold period of time is based on a number of erase/write cycles endured by the first memory block.

5. The method of claim 1, wherein refreshing the data in the first memory block further comprises:

reading the data from the first memory block; and

rewriting the data to the first memory block.

6. The method of claim 1, wherein the data is transient data.

7. The method of claim 1, further comprising:

partitioning the non-volatile memory into a plurality of retention regions, wherein the plurality of retention regions includes a first retention region and a second retention region,

wherein the first retention region comprises the first memory block, and

wherein the second retention region comprises the second memory block.

8. The method of claim 7, wherein:

the first retention region is configured to store data having a first expected storage duration;

the second retention region is configured to store data having a second expected storage duration; and

the first expected storage duration is less than the second expected storage duration.

9. The method of claim 1, wherein a number of erase/write cycles endured by the first memory block is higher than a number of erase/write cycles endured by the second memory block.

10. The method of claim 1, wherein the non-volatile memory is a NAND flash memory.

11. A non-volatile memory device comprising:

a non-volatile memory comprising a first memory block and a second memory block; and

a memory controller configured to

write data in the first memory block,

subsequent to writing the data in the first memory block, determine that the data written in the first memory block needs to be refreshed, and

based on determining that the data written in the first memory block needs to be refreshed,

(i) if the first memory block has endured at least a threshold number of erase/write cycles, relocate the data from the first memory block to the second memory block, and

(ii) if the first memory block has endured less than the threshold number of erase/write cycles, refresh the data in the first memory block.

12. The non-volatile memory device of claim 11, wherein the memory controller is configured to determine that the data written in the first memory block needs to be refreshed by:

determining a time that has elapsed since the data was last written or last refreshed in the first memory block;

determining a number of erase/write cycles endured by the first memory block; and

based on (i) the time that has elapsed since the data was last written or last refreshed in the first memory block and (ii) the number of erase/write cycles endured by the first memory block, determining that the data written in the first memory block needs to be refreshed.

13. The non-volatile memory device of claim 11, wherein the memory controller is configured to determine that the data written in the first memory block needs to be refreshed by:

determining that the data is written in the first memory block, without having been refreshed, for at least a threshold period of time; and

based on determining that the data is written in the first memory block, without having been refreshed, for at least the threshold period of time, determining that the data written in the first memory block needs to be refreshed.

14. The non-volatile memory device of claim 13, wherein the threshold period of time is based on a number of erase/write cycles endured by the first memory block.

15. The non-volatile memory device of claim 11, wherein the memory controller is configured to refresh the data in the first memory block by:

reading the data from the first memory block; and

rewriting the data to the first memory block.

16. The non-volatile memory device of claim 11, wherein the data is transient data.

17. The non-volatile memory device of claim 11, wherein the memory controller is further configured to:

partition the non-volatile memory into a plurality of retention regions, wherein the plurality of retention regions includes a first retention region and a second retention region,

wherein the first retention region comprises the first memory block, and

wherein the second retention region comprises the second memory block.

18. The non-volatile memory device of claim 17, wherein:

the first retention region is configured to store data having a first expected storage duration;

the second retention region is configured to store data having a second expected storage duration; and

the first expected storage duration is less than the second expected storage duration.

19. The non-volatile memory device of claim 11, wherein a number of erase/write cycles endured by the first memory block is higher than a number of erase/write cycles endured by the second memory block.

20. The non-volatile memory device of claim 11, wherein the non-volatile memory is a NAND flash memory.