Method and system for accessing a flash memory device

• US 8,743,610 B2
• Filed: 06/29/2011
• Issued: 06/03/2014
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US13/171,667
• Publication Number:
  US 20110255339A1
• Time in Patent Office: 1,070 Days
• Field of Search: 365/221, 365/219
• US Class Current: 365/185.11
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A semiconductor memory device comprising:

a plurality of flash memory blocks, each of the flash memory blocks having respective row decoding circuitry and respective sense amplifier circuitry; and

an at least one interface, operable to;

i) commonly receive both address and command data at an input port of the at least one interface;

ii) address the flash memory blocks; and

iii) initiate operations performed in at least two of the flash memory blocks in overlapping time periods, and

the at least one interface and the flash memory blocks being provided in a single chip of the semiconductor memory device.

2. The semiconductor memory device of claim 1, wherein the at least one interface is operable to communicate data serially.

3. The semiconductor memory device of claim 1, wherein the at least one interface comprises an output data port.

4. The semiconductor memory device of claim 3, wherein the input port is a unidirectional input data port, and the output data port is a unidirectional output data port.

5. The semiconductor memory device of claim 1, wherein one of the operations is initiated in an at least one of the flash memory blocks while a second and previous operation of the operations is being executed in another of the flash memory blocks.

6. The semiconductor memory device of claim 1, wherein the operations include at least two of page read, program and erase operations.

7. The semiconductor memory device of claim 1, wherein the operations include data transfer operations.

8. The semiconductor memory device of claim 1, wherein the operations include data transfer operations, and at least one of page read, program and erase operations.

9. The semiconductor memory device of claim 1, wherein the operations are initiated through two or more interfaces.

10. The semiconductor memory device of claim 1, wherein the plurality of flash memory blocks is more than two flash memory blocks.

11. The semiconductor memory device of claim 10, wherein the more than two flash memory blocks is more than two flash memory banks.

12. The semiconductor memory device of claim 1, wherein the at least one interface is independently controllable to access any address in any of the flash memory blocks.

13. The semiconductor memory device of claim 12, wherein the at least one interface is further independently controllable to access any row in any of the flash memory blocks.

14. The semiconductor memory device of claim 12, wherein the at least one interface is further independently controllable to access any column in any of the flash memory blocks.

15. The semiconductor memory device of claim 1, wherein the flash memory blocks are flash memory banks.

16. The semiconductor memory device of claim 15, wherein the flash memory banks are NAND flash memory banks.

17. A method carried out in a semiconductor memory device having a plurality of flash memory blocks, each of the flash memory blocks having respective row decoding circuitry and respective sense amplifier circuitry, and the method comprising:

commonly receiving both address and command data at an input port of an interface;

initiating, using the interface, operations in at least two of the flash memory blocks; and

performing the operations in overlapping time periods and in a single chip of the semiconductor memory device that includes the flash memory blocks, and

wherein each of the operations is performed in a respective one of the at least two flash memory blocks.

18. The method of claim 17, wherein the operations include at least two of page read, program and erase operations.

19. The method of claim 17, wherein the operations include data transfer operations.

20. The method of claim 17, wherein the operations include data transfer operations, and at least one of page read, program and erase operations.

21. The method of claim 17, wherein the semiconductor memory device further includes at least two interfaces, the interface being one of the at least two interfaces.

22. The method of claim 17, wherein the interface is operable to communicate data serially.

23. The method of claim 17, wherein the interface comprises an output data port.

24. The method of claim 17, wherein the flash memory blocks are flash memory banks.