Methods for coordinated signal reception across integrated circuit boundaries

• US 8,743,852 B2
• Filed: 01/11/2012
• Issued: 06/03/2014
• Est. Priority Date: 01/14/2011
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Mujtaba, Syed A., Chaudhary, Madhusudan, Elangovan, Thanigaivelu, Anantharaman, Karthik, Dou, Weiping, Mahe, Isabel G.
• Primary Examiner(s): ABELSON, RONALD B
• Application Number:
  US13/347,925
• Publication Number:
  US 20130016632A1
• Time in Patent Office: 874 Days
• Field of Search: 370/229, 370/328, 370/329, 370/339, 370/463, 370/311
• US Class Current: 370/339
• CPC Class Codes: H04B 1/44 Transmit/receive switching
• CPC Class Codes: H04B 7/0608 Antenna selection according to transmission parameters
• CPC Class Codes: H04B 7/0689 using different transmission schemes, at least one of them being a diversity transmission scheme
• CPC Class Codes: H04B 7/0802 using antenna selection H04B7/0868 takes precedence; antenna beam directivity switching H01Q3/24
• CPC Class Codes: H04W 52/02 Power saving arrangements in wired systems H04L12/12; signaling of mobile application services, e.g. low battery notifications H04W4/20
• CPC Class Codes: H04W 52/028 switching on or off only a part of the equipment circuit blocks
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A wireless electronic device having first and second baseband processors is provided. In one suitable arrangement, radio-frequency power splitters and adjustable low noise amplifiers may be form in the receive paths. The use of power splitters allow signals associated with the first and second baseband processors to be received in parallel. In another suitable arrangement, radio-frequency switches are used in place of the power splitters. The states of the switches may be controlled using at least one of the first and second baseband processors. The use of switches instead of power splitters requires that wake periods associated with the first baseband processor and wake periods associated with the second baseband processor are non-overlapping. To ensure minimal wake period collision, a wake period associated with the second baseband processor may be positioned at a midpoint between two successive wake periods associated with the first baseband processor.

Claims

1. A wireless electronic device comprising:

at least one antenna;

a first baseband processor integrated circuit coupled to the antenna, wherein the first baseband processor integrated circuit is operable in a first baseband processor sleep state from which the first baseband processor integrated circuit awakes for a first wake period;

a second baseband processor integrated circuit coupled to the antenna, wherein the second baseband processor integrated circuit is operable in a second baseband processor sleep state from which the second baseband processor integrated circuit awakes for a second wake period and is operable to send control signals to the first baseband processor integrated circuit to avoid collisions between the first and second wake periods;

a first transceiver circuit coupled between the first baseband processor integrated circuit and the antenna; and

a second transceiver circuit coupled between the second baseband processor integrated circuit and the antenna.

2. The wireless electronic device defined in claim 1 further comprising:

an applications processor integrated circuit that is coupled to the first and second baseband processor integrated circuits.

3. The wireless electronic device defined in claim 1 further comprising:

a radio-frequency diplexer that is coupled between the antenna and the first transceiver circuit and that is coupled between the antenna and the second transceiver circuit.

4. The wireless electronic device defined in claim 3 further comprising:

a first radio-frequency duplexer that is coupled between the radio-frequency diplexer and the first transceiver circuit; and

a second radio-frequency duplexer that is coupled between the radio-frequency diplexer and the second transceiver circuit.

5. The wireless electronic device defined in claim 3 further comprising:

at least a first radio-frequency switch that switchably couples a selected one of the first and second transceiver circuits to the radio-frequency diplexer, wherein the first radio-frequency switch is configured to pass uplink radio-frequency signals; and

at least a second radio-frequency switch that switchably couples the radio-frequency diplexer to a selected one of the first and second transceiver circuits, wherein the second radio-frequency switch is configured to pass downlink radio-frequency signals and wherein the first and second radio-frequency switches are controlled by the second baseband processor integrated circuit.

6. The wireless electronic device defined in claim 1, wherein the first and second baseband processor integrated circuits comprise cellular baseband processor integrated circuits operable to support cellular radio access technologies.

7. A method for operating an electronic device with first and second baseband processor integrated circuits and with at least first and second antennas, wherein the first and second baseband processor integrated circuits support corresponding sleep states, wherein the first baseband processor integrated circuit awakens from its sleep state during a first wake period and the second baseband processor integrated circuit awakens from its sleep state during a second wake period, the method comprising:

conveying information between the first and second baseband processor integrated circuits using inter-processor communications to avoid wakeup time collisions between the first and second baseband processor integrated circuits; and

when the first wake period exceeds a predetermined amount of time, using the first antenna to handle the first baseband processor active traffic mode and using the second antenna to handle the second baseband processor active traffic mode.

8. The method defined in claim 7 wherein conveying the information between the first and second baseband processor integrated circuits comprises conveying control signals between the first and second baseband processor integrated circuits to ensure that the first and second wake periods are non-overlapping in time.

9. The method defined in claim 8 further comprising:

during the first wake period, monitoring for first paging signals associated with the first baseband processor integrated circuit; and

during the second wake period, monitoring for second paging signals associated with the second baseband processor integrated circuit.

10. The method defined in claim 9 further comprising:

in response to detecting the first paging signals during the first wake period, placing the first baseband processor integrated circuit in a first baseband processor active traffic mode; and

in response to detecting the second paging signals during the second wake period, placing the second baseband processor integrated circuit in a second baseband processor active traffic mode.

11. The method defined in claim 10 further comprising:

when the first wake period exceeds the predetermined amount of time, preventing the second baseband processor integrated circuit from awakening from its sleep state.

12. The method defined in claim 10 wherein the first and second baseband processor integrated circuits comprise cellular baseband processor integrated circuits, wherein placing the first baseband processor integrated circuit in the first baseband processor active traffic mode comprises establishing a live voice call, and wherein placing the second baseband processor integrated circuit in the second baseband processor active traffic mode comprises establishing an active data session.