Header processing engine
First Claim
1. A header processing engine comprising:
- a command memory;
a header recognizer configured to parse headers of a data packet stored at a buffer so as to identify the type and position of each header in the data packet;
a constructor unit having read access to the headers of the data packet; and
a processor including an execution pipeline;
the header recognizer being further configured to, for each header;
(a) select in dependence on the type of the header one or more commands stored at the command memory; and
(b) form one or more messages for the constructor unit identifying the selected commands and the position of the header in the data packet;
wherein the constructor unit is configured to receive the messages and execute the commands identified therein, the commands selected for the headers of the data packet being collectively such as to, when executed by the constructor unit, cause the constructor unit to generate a data structure which is such as to be operable to cause the processor to effect processing of the headers of the data packet without accessing the data packet at the buffer.
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Accused Products
Abstract
Roughly described, a header processing engine for a network interface device has a header recognizer to parse the headers of a data packet stored at a buffer to identify the type and position of each header in the packet; a constructor unit; and a processor including an execution pipeline. The header recognizer is configured to, for each header: select in dependence on the header type commands stored at a command memory; and form one or more messages for the constructor unit identifying the selected commands and the position of the header in the data packet. The commands selected for the packet headers are collectively such as to, if executed by the constructor unit, cause the constructor unit to generate a data structure which operates to cause the processor to process of the packet headers without accessing the data packet at the buffer.
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Citations
54 Claims
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1. A header processing engine comprising:
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a command memory; a header recognizer configured to parse headers of a data packet stored at a buffer so as to identify the type and position of each header in the data packet; a constructor unit having read access to the headers of the data packet; and a processor including an execution pipeline; the header recognizer being further configured to, for each header; (a) select in dependence on the type of the header one or more commands stored at the command memory; and (b) form one or more messages for the constructor unit identifying the selected commands and the position of the header in the data packet; wherein the constructor unit is configured to receive the messages and execute the commands identified therein, the commands selected for the headers of the data packet being collectively such as to, when executed by the constructor unit, cause the constructor unit to generate a data structure which is such as to be operable to cause the processor to effect processing of the headers of the data packet without accessing the data packet at the buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A header processing engine for performing header processing of a sequence of data packets each having multiple headers, the header processing engine comprising:
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a header recognizer configured to parse the multiple headers of each data packet in a sequence of data packets and, for each data packet, form one or more messages indicating the type and position of each header in the data packet, the header recognizer being configured to parse the data packets in sequence; and a processor configured to perform header processing on each data packet of the sequence in dependence on the one or more messages formed for that data packet and provide processed data packets in sequence at an output of the processor; wherein the header recognizer and the processor are configured to operate in parallel so as to allow the processor to perform header processing on the data packets out of sequence. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30)
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31. A header processing engine for performing header processing of a sequence of data packets stored at a buffer, each of the data packets in the sequence having multiple headers and the header processing engine comprising:
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a processor having an execution pipeline; and a pre-processor unit configured to parse headers of a data packet stored at the buffer and, in dependence on the types of headers in the data packet, form a data structure identifying a set of instructions, the data structure being such as to be operable to cause the processor to effect processing of the headers of the data packet without accessing the data packet stored at the buffer;
wherein the processor is configured to access the data structure and execute the said set of instructions so as to process the headers of the data packet. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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48. A processor configured for processing network data packets, the processor comprising:
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an instruction memory storing a plurality of instruction sequences; a processor memory for storing a plurality of instruction references and sets of state of the processor, each instruction reference identifying an instruction sequence stored at the instruction memory and each set of state corresponding to an instruction reference; and an execution pipeline operable to execute an instruction sequence identified by an instruction reference using the corresponding set of state stored at the processor memory, an instruction sequence and its corresponding state defining an execution thread for processing a particular network data packet; the processor being configured to, during processing of a first network data packet by executing an instruction sequence identified by a first instruction reference, switch execution threads so as to process a second network data packet by; writing the state of the execution pipeline to a first set of state at the processor memory; loading a second set of state into the execution pipeline from the processor memory; and executing a second instruction sequence identified by an instruction reference corresponding to the second set of state; wherein the processor is configured to switch execution threads on initiating execution of one or more predetermined instructions in an instruction sequence. - View Dependent Claims (49, 50, 51, 52, 53)
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54. A method for switching between execution threads at a processor configured for processing network data packets, the method comprising:
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processing a first network data packet by executing by an execution pipeline of the processor a first instruction sequence identified by a first instruction reference stored in a memory of the processor; pausing the execution pipeline; writing a state of the execution pipeline to a first set of state in the processor memory; loading a second set of state into the execution pipeline from the processor memory; and executing in the execution pipeline a second instruction sequence identified by a second instruction reference stored in the processor memory, so as to effect processing of a second network data packet, wherein the first instruction sequence and second instruction sequence correspond to execution threads for processing respectively the first and second network packets.
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Specification