Digital signal conditioning

• US 8,744,025 B2
• Filed: 08/30/2010
• Issued: 06/03/2014
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: BAE Systems Information and Electronic Systems Integration Incorporated (BAE Systems Plc)
• Original Assignee: BAE Systems Information Solutions Incorporated (BAE Systems Plc)
• Inventors: Lowdermilk, Robert W., Vuletic, Dragan, Harris, Fredric J., Tammen, Michael
• Primary Examiner(s): Vlahos, Sophia
• Application Number:
  US13/126,876
• Publication Number:
  US 20110206163A1
• Time in Patent Office: 1,373 Days
• Field of Search: 702/75, 702/76, 702/77, 702/74, 342/76.19, 342/76.21, 342/76.22, 342/76.24, 375/267, 375/346, 375/349, 375/351
• US Class Current: 375/349
• CPC Class Codes: G01R 23/16 Spectrum analysis; Fourier analysis

Abstract

Methods, systems and other embodiments associated with pre-processing a signal for spectral analysis are presented. A system for pre-processing a digital input signal includes a digital down converter (DDC), an interpolator, and a series of down samplers. The DDC modulates the digital input signal to create a down converted signal. The interpolator re-samples the down converted signal to produce a re-sampled signal. The series of down samplers produces down sampled signals. The multiplexer selects one of the digital input signal, the down converted signal, and the down sampled signals and routes the selected signal to an output line.

Claims

1. A system for pre-processing a digital input signal comprising:

a digital down converter (DDC) configured to down convert and down sample at a DDC sample rate a spectral component of the digital input signal to baseband, while reducing bandwidth and sample rate to create a down converted signal at baseband;

an interpolator configured to re-sample the down converted signal to produce a re-sampled signal with a new sample rate, wherein a dynamic range of the digital input signal is preserved and the new sample rate is different than the DDC sample rate;

two or more down samplers configured to produce two or more down sampled signals associated with the down samplers, wherein the two or more down samplers are connected in series, with the re-sampled signal input to a first one of the two or more down samplers, wherein the two or more down sampled signals are output from each of the two or more down samplers connected in series; and

a multiplexer configured to multiplex one of the group of;

the digital input signal, the down converted signal, and one of the two or more down sampled signals to an output line.

2. The system of claim 1 wherein the sample rate of the DDC results in a 4-to-1 sample reduction.

3. The system of claim 1 wherein the two or more down samplers are 2-to-1 down samplers.

4. The system of claim 1 wherein the interpolator is an M-path polyphase filter bank, wherein M is an integer.

5. The system of claim 4 wherein the M-Path polyphase filter bank performs interpolation based, at least in part, on a Taylor series correction of the down converted signal.

6. The system of claim 1 wherein the digital input signal is a real input signal and not a quadrature based signal.

7. The system of claim 1 wherein the output line is configured to be connected to a spectrum analyzer input buffer.

8. The system of claim 1 wherein the interpolator comprises:

one or more finite impulse response (FIR) filters;

one or more accumulators; and

wherein the interpolator is configured to operate on the down converted signal with the one or more FIR filters to produce filter values, wherein the filter values are accumulated in the one or more accumulators to produce accumulated values, and wherein the re-sampled signal is based, at least in part, on the filter values and accumulator values.

9. The system of claim 1 wherein the interpolator is configured to produce the re-sampled signal based, at least in part, on a modulo (MOD) 32 function.

10. The system of claim 1 wherein the interpolator is configured to produce derivative weights of the down converted signal and configured to produce interpolator weights of the down converted signal, and wherein the re-sampled signal is based, at least in part, on the derivative weights and the interpolator weights.

11. The system of claim 1 wherein the interpolator is configured to change the DDC sample rate to a fractional ratio between 0.5 and 2.0 so that 0.5<

DDC sample rate/new sample rate<

2.0.

12. A method of digital signal conditioning comprising:

down converting and down sampling a received input signal at a digital down converter (DDC) sample rate to produce a down converted signal;

determining a desired FFT rate corresponding to an FFT length of a FFT logic;

using the desired FFT rate as an output rate of a series of down samplers connected back-to-back and calculating down sampler input values of the series of down samplers until a specific down sampler input value of one of the down samplers is the closest to the DDC sample rate as compared to the other down sampler input values of the series of down samplers, wherein the specific down sampler input value is a value of a desired arbitrary resampler sample rate;

resampling the down converted signal at the desired arbitrary resampler sample rate to produce a resampled signal, wherein a bandwidth of the down converted signal is preserved and the desired arbitrary resampler sample rate is different than the DDC sample rate;

inputting the resampled signal into the series of down samplers;

outputting to the FFT logic the output value of a down sampler of the series of down samplers that produces the desired FFT rate.

13. The method of claim 12 wherein the resampling comprises:

filtering the down converted signal with an M-path polyphase filter bank, wherein M is an integer;

generating the resampled signal based, at least in part, on a result of the filtering.

14. The method of claim 12 wherein the resampling comprises:

passing the down converted signal through a finite impulse response (FIR) filter; and

generating the resampled signal based, at least in part, on an output of the FIR filter.

15. The method of claim 12 further comprising:

receiving the received input signal from an analog-to-digital converter (ADC).

16. The method of claim 15 wherein the receiving further comprises:

receiving the received input signal that is an intermediate frequency (IF) signal.

17. The method of claim 12 further comprising:

transferring the output value of the down sampler that produces the desired FFT rate to an input buffer of a spectrum analyzer.

18. The method of claim 12 wherein the down converting and down sampling comprises:

passing the input signal through a 4-to-1 digital down converter.

19. The method of claim 12 wherein the series of down samplers is a series of 2-to-1 down samplers.

20. A method comprising:

down converting and down sampling an input signal at a DDC sample rate to produce a down converted signal;

determining a desired FFT rate;

sequentially doubling the desired FFT rate creating doubled values until a doubled value exceeds the DDC sample rate;

assigning a created doubled value that is the closest to the DDC sample rate as a desired arbitrary resampler rate;

resampling the down converted signal at the desired arbitrary resampler rate to produce a resampled signal, wherein a bandwidth of the down converted signal is preserved and the DDC sample rate is different than the desired arbitrary resampler rate;

passing the resampled signal through a series of 2-to-1 down samplers to produce a new signal at the desired FFT rate; and

inputting the new signal into a spectrum analyzer.