Shift register circuit

• US 8,744,038 B2
• Filed: 09/27/2012
• Issued: 06/03/2014
• Est. Priority Date: 09/28/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Hirose, Atsushi
• Primary Examiner(s): TRA, ANH QUAN
• Application Number:
  US13/628,437
• Publication Number:
  US 20130077735A1
• Time in Patent Office: 614 Days
• Field of Search: 377/64, 377/68, 377/73, 377/74, 377/78, 377/79, 327/108, 327/112, 326/95, 326/98
• US Class Current: 377/64
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A shift register circuit including a logic circuit capable of controlling the threshold voltage of a transistor and outputting a signal corresponding to an input signal by changing only the potential of a back gate without changing the potential of a gate is provided. In a shift register circuit including a logic circuit with a first transistor and a second transistor having the same conductivity type, a first gate electrode of the first transistor is connected to a source electrode or a drain electrode of the first transistor, an input signal is supplied to a second gate electrode of the first transistor, a clock signal is supplied to a gate electrode of the second transistor, and the first gate electrode and the gate electrode are formed from the same layer.

Claims

1. A logic circuit comprising:

a first transistor having a conductivity, the first transistor comprising;

a first gate electrode;

a source electrode or a drain electrode electrically connected to the first gate electrode; and

a second gate electrode electrically connected to a first wiring; and

a second transistor having the conductivity, the second transistor comprising a third gate electrode electrically connected to a second wiring,

wherein an input signal is supplied to the first wiring, and

wherein a clock signal is supplied to the second wiring.

2. The logic circuit according to claim 1,

wherein the first transistor and the second transistor are n-channel transistors.

3. The logic circuit according to claim 1,

wherein the first gate electrode and the third gate electrode are formed from a same layer.

4. A shift register circuit comprising the logic circuit according to claim 1.

5. A display device comprising the shift register circuit according to claim 4.

6. An electronic device comprising the display device according to claim 5.

7. A logic circuit comprising:

a first transistor having a conductivity, the first transistor comprising;

a first gate electrode;

a source electrode or a drain electrode electrically connected to the first gate electrode;

a first semiconductor film over the first gate electrode; and

a second gate electrode over the first semiconductor film, the second gate electrode being electrically connected to a first wiring; and

a second transistor having the conductivity, the second transistor comprising;

a third gate electrode electrically connected to a second wiring; and

a second semiconductor film over the third gate electrode,

wherein an input signal is supplied to the first wiring, and

wherein a clock signal is supplied to the second wiring.

8. The logic circuit according to claim 7,

wherein the first transistor and the second transistor are n-channel transistors.

9. The logic circuit according to claim 7,

wherein the first semiconductor film and the second semiconductor film are formed from a same layer.

10. The logic circuit according to claim 7,

wherein the first semiconductor film and the second semiconductor film are oxide semiconductor films.

11. A shift register circuit comprising the logic circuit according to claim 7.

12. A display device comprising the shift register circuit according to claim 11.

13. An electronic device comprising the display device according to claim 12.

14. A logic circuit comprising:

a first transistor having a conductivity, the first transistor comprising;

a first gate electrode;

a gate insulating film over the first gate electrode;

a first semiconductor film over the gate insulating film;

a source electrode and a drain electrode over the first semiconductor film;

an interlayer insulating film over the source electrode and the drain electrode; and

a second gate electrode over the interlayer insulating film, the second gate electrode being electrically connected to a first wiring; and

a second transistor having the conductivity, the second transistor comprising;

a third gate electrode electrically connected to a second wiring;

the gate insulating film over the third gate electrode; and

a second semiconductor film over the gate insulating film,

wherein the first gate electrode is electrically connected to the source electrode or the drain electrode,

wherein an input signal is supplied to the first wiring, and

wherein a clock signal is supplied to the second wiring.

15. The logic circuit according to claim 14,

wherein the first transistor and the second transistor are n-channel transistors.

16. The logic circuit according to claim 14,

wherein a thickness of the gate insulating film is smaller than a thickness of the interlayer insulating film.

17. The logic circuit according to claim 14,

wherein the first semiconductor film and the second semiconductor film are formed from a same layer.

18. The logic circuit according to claim 14,

wherein the first semiconductor film and the second semiconductor film are oxide semiconductor films.

19. A shift register circuit comprising the logic circuit according to claim 14.

20. A display device comprising the shift register circuit according to claim 19.

21. An electronic device comprising the display device according to claim 20.