Integrated circuit with an adaptable contact pad reconfiguring architecture

• US 8,744,368 B2
• Filed: 12/30/2011
• Issued: 06/03/2014
• Est. Priority Date: 08/17/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kothari, Love, Bennett, James, Zhang, Zhongmin
• Primary Examiner(s): Milord, Marceau
• Application Number:
  US13/340,873
• Publication Number:
  US 20130043939A1
• Time in Patent Office: 886 Days
• Field of Search: 455/67.11, 455/78, 455/67.14, 455/80, 455/84, 455/118, 455/333, 455/207, 455/314, 455/323, 455/226.1, 455/115.1, 455/115.2, 375/224, 375/349, 327/564
• US Class Current: 455/67.11
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3228 Monitoring task completion, e.g. by use of idle timers, stop commands or wait commands
• CPC Class Codes: G06F 12/14 Protection against unauthorised use of memory or access to memory
• CPC Class Codes: G06F 21/44 Program or device authentication
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 2005/00026 controlled by an analog electrical signal, e.g. obtained after conversion by a D/A converter
• CPC Class Codes: H03K 2005/00058 controlled by a digital setting
• CPC Class Codes: H03K 3/0315 Ring oscillators
• CPC Class Codes: H03K 3/037 Bistable circuits
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/097 using a comparator for comparing the voltages obtained from two frequency to voltage converters
• CPC Class Codes: H03L 7/0997 Controlling the number of delay elements connected in series in the ring oscillator

Abstract

An apparatus and method are disclosed for providing test mode contact pad reconfigurations that expose individual internal functional modules or block groups in an integrated circuit for testing and for monitoring. A plurality of switches between each functional module switches between passing internal signals among the blocks and passing in/out signals external to the block when one or more contact pads are strapped to input a pre-determined value. Another set of switches between the functional modules and input/output contact pads switch between functional inputs to and from the functional modules and monitored signals or input/output test signals according to the selected mode of operation.

Claims

1. An integrated circuit, comprising:

a switching interconnect module;

a controller module, coupled to the switching interconnect module, configured to cause the switching interconnect module to enter into a testing mode of operation or a monitoring mode of operation; and

a plurality of functional modules, coupled to the switching interconnect module, each of the plurality of functional modules being configured to communicate with the switching interconnect module over a corresponding signal pathway from among a plurality of signal pathways,

wherein the switching interconnect module is configurable to couple a signal pathway from among the plurality of signal pathways to another signal pathway from among the plurality of signal pathways.

2. The integrated circuit of claim 1, further comprising:

a plurality of configurable contact pads; and

a pad allocation module configured to set an operation of the plurality of configurable contact pads and to arrange a plurality of connections between the configurable contact pads and the switching interconnect module,

wherein the switching interconnect module is further configurable to couple the plurality of connections to a functional module from among the plurality of functional modules via its corresponding signal pathway.

3. The integrated circuit of claim 1,

wherein the switching interconnect module is further configurable to cause a first configuration of the plurality of signal pathways to isolate at least one functional module from among the plurality of functional modules in the testing mode of operation and to cause a second configuration of the plurality of signal pathways to allow for monitoring of signals within one of the plurality of signal pathways in the monitoring mode of operation.

4. The integrated circuit of claim 1, wherein the controller module is further configured to execute a testing routine in the testing mode of operation, the testing routine being used to determine whether at least one functional module from among the plurality of functional modules operates as expected.

5. The integrated circuit of claim 4, wherein the testing routine includes an instruction to be executed by the plurality of functional modules and a parameter that is to be used by the instruction.

6. The integrated circuit of claim 5, wherein the parameter includes pattern data.

7. The integrated circuit of claim 1, further comprising:

a second integrated circuit configured to operate in a slave mode of operation, wherein the controller module is further configured to operate in a master mode of operation to control configuration and operation of the second integrated circuit.

8. The integrated circuit of claim 1, wherein the plurality of functional modules are selected from a group consisting of:

a radio frequency (RF) module;

a power management unit (PMU) module; and

a baseband (BB) module.

9. An integrated circuit, comprising:

a plurality of modules, the plurality of modules including a radio frequency (RF) module and a baseband (BB) module;

a controller module configured to cause the integrated circuit to enter into one of a plurality of modes of operation; and

a switching interconnect module, responsive to the controller module, configured to;

isolate the RF module from a first subset of modules from among the plurality of modules in a first mode of operation,

isolate the BB module from a second subset of modules from among the plurality of modules in a second mode of operation, and

couple the RF module to the BB module in a third mode of operation.

10. The integrated circuit of claim 9, wherein the switching interconnect module comprises:

a plurality of switchable paths,

wherein a first path and a second path from among the plurality of switchable paths are configurable to be conducting during the first mode of operation,

wherein a third path and a fourth path from among the plurality of switchable paths are configurable to be conducting during the second mode of operation, and

wherein a fifth path and a sixth path from among the plurality of switchable paths are configurable to be conducting during the third mode of operation.

11. The integrated circuit of claim 10, wherein the first path is configured to couple an output of the RF module to a first testing signal,

wherein the second path is configured to couple a second testing signal to an input of the RF module,

wherein the third path is configured to couple the first testing signal to an input of the BB module,

wherein the fourth path is configured to couple an output of the BB module to the second testing signal,

wherein the fifth path is configured to couple the output of the RF module to the input of the BB module, and

wherein the sixth path is configured to couple the output of the BB module to the input of the RF module.

12. The integrated circuit of claim 11, wherein the fifth path is further configured to couple the output of the RF module to the first testing signal, and

wherein the sixth path is further configured to couple the output of the BB module to the second testing signal.

13. The integrated circuit of claim 9, further comprising:

a plurality of configurable contact pads being assigned to one of the plurality of functional blocks,

wherein a first set of configurable contact pads from among the plurality of configurable contact pads is reassigned to the RF functional block in the first mode of operation, and

wherein a second set of configurable contact pads from among the plurality of configurable contact pads is reassigned to the BB functional block in the second mode of operation.

14. The integrated circuit of claim 13, wherein a third set of configurable contact pads from among the plurality of configurable contact pads is reassigned to allow to monitor signals between the RF functional block and the BB functional block in the third mode of operation.

15. The integrated circuit of claim 13, further comprising:

a plurality of pins, each pin from among the plurality of pins being coupled to a configurable contact pad from among the plurality of configurable contact pads.

16. The integrated circuit of claim 9, wherein the switching interconnect module is further configured to:

isolate an input and an output of the RF functional block from another functional block from among the plurality of functional blocks in the first mode of operation,

isolate an input and an output of the BB functional block from another functional block from among the plurality of functional blocks in the second mode of operation, and

couple an input and an output of the RF functional block to the BB functional block in the third mode of operation,

wherein the RF functional block is further configured to provide a clock to the BB functional block in the second mode of operation.

17. An integrated circuit, comprising:

a switching interconnect module;

a plurality of core modules, each of the plurality of core modules being configured to communicate with the switching interconnect module over a corresponding signal pathway from among a plurality of signal pathways, each of the plurality of core modules including;

a second switching interconnect module, and

a plurality of functional modules coupled to the second switching interconnect module, each of the plurality of functional modules being configured to communicate with the second switching interconnect module over a corresponding signal pathway from among a plurality of second signal pathways,

wherein the second switching interconnect module is configurable to couple a signal pathway from among the second plurality of signal pathways to another signal pathway from among the second plurality of signal pathways,

wherein the switching interconnect module is configurable to couple a signal pathway from among the plurality of signal pathways to another signal pathway from among the plurality of signal pathways.

18. The integrated circuit of claim 17, further comprising:

a plurality of configurable contact pads,

wherein each of the plurality of core modules further includes;

a pad allocation module configured to set an operation of a corresponding set of the plurality of configurable contact pads and to arrange a plurality of connections between the corresponding set of configurable contact pads and the second switching interconnect module,

wherein the second switching interconnect module is further configurable to couple the plurality of connections to a functional module from among the plurality of functional modules via its corresponding second signal pathway.

19. The integrated circuit of claim 17, wherein one of the plurality of core modules is configured to operate as a master core module to control overall configuration and operation of another core module from among the plurality of core modules, the other core module being configured to operate as a slave core module.

20. The integrated circuit of claim 19, wherein the master core module is configured to provide an instruction and a parameter of a testing routine to the slave core module.