Flash memory based storage devices utilizing magnetoresistive random access memory (MRAM) to store control information facilitating wear leveling

• US 8,745,319 B2
• Filed: 02/13/2012
• Issued: 06/03/2014
• Est. Priority Date: 08/08/2008
• Status: Expired due to Fees

• Current Assignee: SPEX Technologies, Inc.
• Original Assignee: Imation Corporation (Glassbridge Enterprises, Inc.)
• Inventors: Langlois, Denis J., Olson, Alan R.
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US13/372,011
• Publication Number:
  US 20120144102A1
• Time in Patent Office: 841 Days
• Field of Search: 711/103, 711/161, 711/202, 711/5, 713/320, 710/52, 365/158
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Claims

1. A storage device comprising:

flash memory comprising a plurality of physical data blocks;

a flash memory controller that controls at least one of addressing, programming, erasing, and reading of the flash memory;

a host interface for communicating with a host device;

a magnetoresistive random access memory (MRAM) buffer electrically connected between the host interface and the flash controller;

a processor that receives commands from the host device via the host interface and coordinates the at least one of addressing, programming, erasing and reading of the flash memory by the flash memory controller; and

MRAM device memory electrically connected to the processor, the MRAM device memory storing control information comprising an erase count table and a flash translation layer table, wherein the erase count table comprises an erase count for each of the plurality of physical data blocks of the flash memory, the control information facilitating wear leveling of the flash memory according to a dynamic algorithm that comprises, upon receiving, from the host device, a write command for a logical address;

scanning a portion of the erase count table corresponding to data blocks of the flash memory that are available to be written to;

selecting an available data block of the flash memory based on its corresponding erase count;

writing data corresponding to the write command to the selected data block;

updating the flash translation layer table to reflect an association between the logical address and a physical address for the selected data block; and

erasing a data block previously associated with the logical address and incrementing an erase count in the erase count table corresponding to the erased data block;

wherein the MRAM buffer receives data via the host interface and stores the data until the data is written to the flash memory under control of the flash memory controller; and

wherein upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

2. The storage device of claim 1, wherein the storage device is a solid state drive (SSD).

3. The storage device of claim 1, wherein the flash memory controller comprises a plurality of flash memory controllers, wherein the storage device further comprises a multiplexer electrically connected between the MRAM buffer and the plurality of flash controllers, and wherein the multiplexer accepts input from the plurality of flash controllers and outputs the input to the host interface.

4. The storage device of claim 1, wherein the MRAM device memory stores control information pertinent to the writing and reading of data to and from the plurality of physical blocks of the flash memory.

5. The storage device of claim 4, wherein the processor causes the control information to be stored in the MRAM device memory without causing writing of the control information to the flash memory.

6. The storage device of claim 1, wherein the processor compares a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be stored in the MRAM buffer when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table.

7. The storage device of claim 1, wherein the control information further facilitates wear leveling of the flash memory according to a static algorithm that comprises:

for at least a subset of the data blocks of the flash memory that are storing data, determining a data block with a minimum erase count, the data block associated with a logical block address in the flash translation layer table;

for at least a subset of the data blocks of the flash memory that are available to be written to, determining a data block with a maximum erase count; and

where a difference between the minimum erase count and the maximum erase count is greater than a predetermined threshold value, copying the data stored in the data block with the minimum erase count to the data block with the maximum erase count, erasing the data in the data block with the minimum erase count, updating the flash translation layer table to reflect that the logical address associated the data block with the minimum erase count is now associated with a physical address for the data block with the maximum erase count, and incrementing an erase count in the erase count table corresponding to the data block with the minimum erase count.

8. The storage device of claim 7, wherein the static algorithm further comprises:

periodically determining an idle time for each of the subset of the data blocks of the flash memory that are storing data, the idle time being the period of inactivity for the corresponding data block; and

comparing the determined idle times to a predetermined threshold idle time, and if none of the determined idle times are greater than the predetermined threshold idle time, placing the static algorithm in a standby state for a predetermined period of time.

9. A storage device comprising:

flash memory comprising a plurality of physical data blocks;

a flash memory controller that controls at least one of addressing, programming, erasing, and reading of the flash memory;

a host interface for communicating with a host device;

a magnetoresistive random access memory (MRAM) buffer electrically connected between the host interface and the flash controller;

a processor that receives commands from the host device via the host interface and coordinates the at least one of addressing, programming, erasing and reading of the flash memory by the flash memory controller; and

MRAM device memory electrically connected to the processor, the MRAM device memory storing control information comprising an erase count table and a flash translation layer table, wherein the erase count table comprises an erase count for each of the plurality of physical data blocks of the flash memory, the control information facilitating wear leveling of the flash memory according to a static algorithm that comprises;

for at least a subset of the data blocks of the flash memory that are storing data, determining a data block with a minimum erase count, the data block associated with a logical block address in the flash translation layer table;

for at least a subset of the data blocks of the flash memory that are available to be written to, determining a data block with a maximum erase count; and

where a difference between the minimum erase count and the maximum erase count is greater than a predetermined threshold value, copying the data stored in the data block with the minimum erase count to the data block with the maximum erase count, erasing the data in the data block with the minimum erase count, updating the flash translation layer table to reflect that the logical address is now associated with a physical address for the data block with the maximum erase count, and incrementing an erase count in the erase count table corresponding to the erased data block;

wherein the MRAM buffer receives data via the host interface and stores the data until the data is written to the flash memory under control of the flash memory controller; and

wherein upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

10. The storage device of claim 9, wherein the static algorithm further comprises:

periodically determining an idle time for each of the subset of the data blocks of the flash memory that are storing data, the idle time being the period of inactivity for the corresponding data block; and

comparing the determined idle times to a predetermined threshold idle time, and if none of the determined idle times are greater than the predetermined threshold idle time, placing the static algorithm in a standby state for a predetermined period of time.

11. The storage device of claim 9, wherein the storage device is a solid state drive (SSD).

12. The storage device of claim 9, wherein the flash memory controller comprises a plurality of flash memory controllers, wherein the storage device further comprises a multiplexer electrically connected between the MRAM buffer and the plurality of flash controllers, and wherein the multiplexer accepts input from the plurality of flash controllers and outputs the input to the host interface.

13. The storage device of claim 9, wherein the MRAM device memory stores control information pertinent to the writing and reading of data to and from the plurality of physical blocks of the flash memory.

14. The storage device of claim 13, wherein the processor causes the control information to be stored in the MRAM device memory without causing writing of the control information to the flash memory.

15. The storage device of claim 9, wherein the processor compares a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be stored in the MRAM buffer when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table.