Management of non-volatile memory systems having large erase blocks
First Claim
1. In a non-volatile memory having memory cells organized in a plurality of groups of one or more blocks of a minimum number of cells that are simultaneously erasable and storing a given number of pages of data at specified page numbers, a method of updating data in less than the given number of pages of a first programmed group of blocks, comprising:
- designating at least first and second blocks to receive updated data of less than the given number of pages of the first programmed group of blocks,writing data of one or more pages having a number of sequential logical addresses less than a predetermined number to pages of the first designated block, andwriting data of a plurality of pages with a number of sequential logical addresses equal to or in excess of the predetermined number of pages to the second designated block.
1 Assignment
0 Petitions
Accused Products
Abstract
A non-volatile memory system of a type having blocks of memory cells erased together and which are programmable from an erased state in units of a large number of pages per block. If the data of only a few pages of a block are to be updated, the updated pages are written into another block provided for this purpose. Updated pages from multiple blocks are programmed into this other block in an order that does not necessarily correspond with their original address offsets. The valid original and updated data are then combined at a later time, when doing so does not impact on the performance of the memory. If the data of a large number of pages of a block are to be updated, however, the updated pages are written into an unused erased block and the unchanged pages are also written to the same unused block. By handling the updating of a few pages differently, memory performance is improved when small updates are being made. The memory controller can dynamically create and operate these other blocks in response to usage by the host of the memory system.
-
Citations
18 Claims
-
1. In a non-volatile memory having memory cells organized in a plurality of groups of one or more blocks of a minimum number of cells that are simultaneously erasable and storing a given number of pages of data at specified page numbers, a method of updating data in less than the given number of pages of a first programmed group of blocks, comprising:
-
designating at least first and second blocks to receive updated data of less than the given number of pages of the first programmed group of blocks, writing data of one or more pages having a number of sequential logical addresses less than a predetermined number to pages of the first designated block, and writing data of a plurality of pages with a number of sequential logical addresses equal to or in excess of the predetermined number of pages to the second designated block. - View Dependent Claims (2, 3)
-
-
4. In a non-volatile memory having memory cells organized in groups of one or more blocks of a minimum number of cells that are simultaneously erasable and wherein a given number of host units of data are programmed into individual ones of the groups of one or more blocks, a method of updating less than all the data stored in a given group of one or more blocks in response to a host command, comprising:
-
designating at least a first group of one or more blocks to store in sequential physical block locations host units of data within a first range of logical addresses without regard to whether the logical addresses of such data are sequential or not, and designating at least a second group of one or more blocks to store host units of data within a second range of logical addresses with sequential logical addresses therein designated for sequential physical locations with an address offset of zero or more. - View Dependent Claims (5, 6, 7, 8)
-
-
9. A memory system, comprising:
-
an array of non-volatile memory cells organized into a plurality of sub-arrays that individually include addressing, programming and reading circuits, the sub-arrays being divided into units of memory cells that are erased together, the erase units further being divided into units of cells that are programmed together, the programming units being identified by programming unit offset addresses within their erase units, a controller that controls operation of the memory cell array, at least one erase unit within individual ones of the sub-arrays being designated by the controller to store updated data of sequentially addressed programming units of a first group of one or more others of the erase units within individual ones of the sub-arrays in programming units having the same address order as the programming units within said at least one other of the erase units and with an address offset of zero or more, and at least another erase unit within individual ones of the sub-arrays being designated by the controller to store updated data of programming units of a second group of one or more others of the erase units within individual ones of the sub-arrays in pages according to a predetermined sequence without regard to the address sequence or programming unit offset of the programming unit data being updated. - View Dependent Claims (10, 11, 12)
-
-
13. A non-volatile memory system of a type having blocks of memory cells that are simultaneously erasable and which individually store a given number of host units of data, comprising:
-
a first block designated for storage of a number of units of data with sequential logical addresses that is less than a pre-set proportion of the given number, the pre-set proportion being less than the given number; and a controller configured to respond to a plurality of successive host commands to write a number of units of data less than the pre-set proportion of the given number that have sequential logical addresses by writing their data into the first designated block with sequential physical addresses, and configured to respond to host commands to write a number of units of data having sequential logical addresses that is equal to or in excess of the pre-set proportion of said given number by writing their data into a block other than the first designated block. - View Dependent Claims (14, 15, 16)
-
-
17. A non-volatile memory system having memory cells grouped into blocks of memory cells that are simultaneously erasable and which individually store a given number of units of data at individual physical addresses, the logical addresses of received units of data being mapped within the memory system into corresponding physical addresses where the received units of data are stored, comprising:
-
a first block designated to store units of data having a number of sequential logical addresses that is less than a pre-determined fraction of said given number, a second block designated to store units of data having a number of sequential logical addresses that is greater than the fraction of said given number, and a controller that, in response to receipt of a command to write data into the memory system; identifies the number of units of the data that have sequential logical addresses; determines whether the number of such units with sequential logical addresses is less than the fraction; if the number of such units with sequential logical addresses is less than the fraction, then writes the data to the first block; if the number of such units with sequential logical addresses is not less than the fraction, then writes the data to the second block if there is sufficient capacity therein. - View Dependent Claims (18)
-
Specification