Systems and methods for managing end of life in a solid state drive

• US 8,745,449 B2
• Filed: 01/11/2012
• Issued: 06/03/2014
• Est. Priority Date: 05/28/2009
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Dreifus, David L., Warren, Robert W., McKean, Brian
• Primary Examiner(s): Bonzo, Bryce
• Assistant Examiner(s): Mehrmanesh, Elmira
• Application Number:
  US13/347,827
• Publication Number:
  US 20120110376A1
• Time in Patent Office: 874 Days
• Field of Search: 714/47.1, 714/47.2, 714/47.3, 714/54
• US Class Current: 714/47.3
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.

Claims

1. A storage system, the storage system comprising:

a first non-volatile memory portion and a second non-volatile memory portion, wherein the first non-volatile memory portion and the second non-volatile memory portion are addressable in the storage system;

a failure indication circuit operable to identify the first non-volatile memory portion as read only upon determination that a subset of the first non-volatile memory portion is unreliable and the subset of the first non-volatile memory portion is larger than a threshold level;

a time stamp circuit operable to identify a first point in time when the failure indication circuit identified the first non-volatile memory portion as read only; and

an end of life circuit operable to estimate a second point in time based at least in part on the first point in time, wherein the second point in time corresponds to a time when the reliability of the storage system is unreliable.

2. The storage system of claim 1, wherein the storage system further comprises:

a control circuit operable to receive a write request directed to the first non-volatile memory portion, and direct the write request to the second non-volatile memory portion based at least in part on identification of the first non-volatile memory portion as read only.

3. The storage system of claim 2, wherein the first non-volatile memory portion is included in a first solid state drive, wherein the second non-volatile memory portion is included in a second solid state drive, wherein the storage system further comprises:

a system controller communicably coupled to the first solid state drive and the second solid state drive, wherein the end of life circuit is included in the system controller.

4. The storage system of claim 3, wherein the system controller is operable to assure that all data from the first solid state drive is transferred to the second solid state drive before the second time.

5. The storage system of claim 2, wherein the control circuit is implemented as part of an integrated circuit.

6. The storage system of claim 1, wherein the first non-volatile memory portion is included in a first solid state storage device, and wherein the second non-volatile memory portion is included in a second solid state storage device.

7. The storage system of claim 6, wherein the storage system further comprises:

a system controller communicably coupled to the first solid state drive and the second solid state drive, wherein the end of life circuit is included in the system controller.

8. The storage system of claim 7, wherein the system controller is operable to assure that all data from the first solid state drive is transferred to the second solid state drive before the estimated end of life.

9. The storage system of claim 1, wherein the system further comprises:

a mapping circuit operable to map the second non-volatile memory portion to the first non-volatile memory portion based at least in part upon determining that the subset of the first non-volatile memory portion is unreliable.

10. The storage system of claim 9, wherein the mapping circuit is further operable to:

receive a write request directed to the first non-volatile memory portion; and

direct the write request to the second non-volatile memory portion.

11. The storage system of claim 1, wherein the first non-volatile memory portion and the second non-volatile memory portion are implemented as flash memory cells.

12. The storage system of claim 1, wherein the storage system further comprises:

a control circuit operable to receive a write request directed to the subset of the first non-volatile memory portion, and to direct the write request to a subset of the second non-volatile memory portion based at least in part on identification of the first non-volatile memory portion as read only.

13. The storage system of claim 12, wherein the control circuit is further operable to:

receive a read request directed to the first subset of the first non-volatile memory portion; and

direct the read request to the first subset of the first non-volatile memory portion where the read request is received prior to directing the write request to the subset of the second non-volatile memory portion.

14. A storage device, the device comprising:

a first number of memory portions each including a plurality of memory cells, wherein a second number of the first number of memory portions are addressable, and wherein a difference between the first number and the second number is an over provisioned number of memory portions;

a control circuit that includes;

an unreliable block identification circuit, wherein the unreliable block identification circuit is operable to determine that one or more of the first number of memory portions is unreliable, and wherein upon determining that one or more of the first number of memory portions is unreliable the over provisioned number of memory portions is reduced; and

a partial failure indication circuit operable to disallow write access to any of the memory portions upon determination that the over provisioned number of memory portions is less than or equal to a threshold level;

a time stamp circuit operable to identify a first point in time when the partial failure indication circuit disallowed write access to the memory portions; and

an end of life circuit operable to estimate a second point in time when the ability to read one or more of the plurality of memory portions can no longer be guaranteed wherein the second point is time is calculated by adding a time increment to the first point in time.

15. The device of claim 14, wherein the first number of memory portions are non-volatile memory portions.

16. The device of claim 15, wherein the non-volatile memory portions are implemented as flash memory cells.

17. The device of claim 14, wherein the device comprises:

a control circuit operable to receive a write request directed to a first subset of the first number of memory portions, and to direct the write request to a second subset of the first number of memory portions based at least in part on identification of the first subset of the first number of memory portions as read only.

18. The device of claim 17, wherein the control circuit is further operable to:

receive a read request directed to the first subset of the first number of memory portions; and

direct the read request to the first subset of the first number of memory portions where the read request is received prior to directing the write request to the second subset of the of the first number of memory portions.

19. The device of claim 14, wherein the first subset of the first number of memory portions are included in a first solid state drive, and wherein the second subset of the first number of memory portions are included in a second solid state drive.

20. The device of claim 19, wherein the device further comprises:

a system controller communicably coupled to the first solid state drive and the second solid state drive, wherein the end of life circuit is included in the system controller.

21. The device of claim 20, wherein the system controller is operable to assure that all data from the first solid state drive is transferred to the second solid state drive before the estimated end of life.

22. The device of claim 14, wherein the time increment is an estimate of how long data will remain readable after the first point in time.

23. The device of claim 14, wherein the estimate of how long data will remain readable is a predetermined, fixed value.