Deployment of transmission gate logic cells in application specific integrated circuits

• US 8,745,558 B1
• Filed: 01/31/2013
• Issued: 06/03/2014
• Est. Priority Date: 01/31/2013
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Corporation (Broadcom, Inc.)
• Inventors: Garofalo, Joseph, Bartholomew, Barry L., Luo, Mujiang, Rao, You Xin
• Primary Examiner(s): LIN, SUN J
• Application Number:
  US13/755,869
• Time in Patent Office: 488 Days
• Field of Search: 716/100, 716/101, 716/103, 716/104, 716/106, 716/134
• US Class Current: 716/103
• CPC Class Codes: G06F 2111/20 Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

Abstract

A method is provided for designing an integrated circuit. The method includes generating a net list of an integrated circuit design, wherein the net list includes one or more component cells selected from a cell library. The component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells. Each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell. The method further includes auditing the net list to determine if a given sourcing cell in the integrated circuit design has a sufficient driving strength based at least on the driving strength attribute of a transmission gate logic cell being driven by the given sourcing cell.

Claims

1. A method of designing an integrated circuit, comprising:

generating a net list of an integrated circuit design, wherein the net list comprises one or more component cells selected from a cell library, wherein the component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells, wherein each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell; and

auditing the net list to determine if a given sourcing cell in the integrated circuit design has a sufficient driving strength based at least on the driving strength attribute of a transmission gate logic cell being driven by the given sourcing cell,

wherein the generating step and the auditing step are automated steps performed by a computer.

2. The method of claim 1, wherein the auditing step comprises:

identifying, from the net list, a sourcing cell associated with each transmission gate logic cell in the integrated circuit design, and a number of transmission gate logic cells driven by each identified sourcing cell; and

for each sourcing cell in the integrated circuit design, determining if the sourcing cell has a sufficient driving strength, wherein said determining is based at least on the driving strength attribute associated with each transmission gate logic cell being driven by the sourcing cell and a number of transmission gate logic cells being driven by the sourcing cell.

3. The method of claim 1, further comprising, if a given sourcing cell is determined to have an insufficient driving strength, automatically selecting another sourcing cell having a driving strength that is greater than a driving strength of the given sourcing cell.

4. The method of claim 1, wherein the timing characteristic includes a delay from an input port to an output port of the transmission gate logic cell.

5. The method of claim 4, wherein the input port comprises a select port of a combinatorial transmission gate logic cell.

6. The method of claim 4, wherein the input port comprises a data input port of a transmission gate-based flip-flop logic cell.

7. The method of claim 1, wherein the auditing step is implemented by a script that is executed as part of a static timing process of an integrated circuit design tool.

8. A non-transitory computer readable storage medium comprising a program of instructions which, when executed by a computer, perform the method steps of claim 1 for designing an integrated circuit.

9. A computing system, comprising:

a memory to store program instructions for designing an integrated circuit and to store a cell library comprising a plurality of component cells, wherein the component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells, wherein each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell; and

a processor system coupled to the memory, wherein the processor system is operative to execute the stored program instructions to perform a method for designing an integrated circuit, the method comprising;

generating a net list of an integrated circuit design, wherein the net list comprises one or more component cells selected from a cell library, wherein the component cells include transmission gate logic cells and sourcing cells that drive the transmission gate logic cells, wherein each transmission gate logic cell has an associated timing model with a timing characteristic defined as a function of a driving strength attribute of a sourcing cell used to characterize the transmission gate logic cell; and

auditing the net list to determine if a given sourcing cell in the integrated circuit design has a sufficient driving strength based at least on the driving strength attribute of a transmission gate logic cell being driven by the given sourcing cell.

10. The computing system of claim 9, wherein the auditing step comprises:

identifying, from the net list, a sourcing cell associated with each transmission gate logic cell in the integrated circuit design, and a number of transmission gate logic cells driven by each identified sourcing cell; and

for each sourcing cell in the integrated circuit design, determining if the sourcing cell has a sufficient driving strength, wherein said determining is based at least on the driving strength attribute associated with each transmission gate logic cell being driven by the sourcing cell and a number of transmission gate logic cells being driven by the sourcing cell.

11. The computing system of claim 9, wherein if a given sourcing cell is determined to have an insufficient driving strength, the processor system is further operative to execute program instructions for automatically selecting another sourcing cell having a driving strength that is greater than a driving strength of the given sourcing cell.

12. The computing system of claim 9, wherein the timing characteristic includes a delay from an input port to an output port of the transmission gate logic cell.

13. The computing system of claim 12, wherein the input port comprises a select port of a combinatorial transmission gate logic cell.

14. The computing system of claim 12, wherein the input port comprises a data input port of a transmission gate-based flip-flop cell.

15. The computing system of claim 9, wherein the auditing step is implemented by executing a script which is part of a static timing process of an integrated circuit design tool.

16. A method for building a component cell library for an integrated circuit design tool, the method comprising:

building a transmission gate logic cell having a sourcing cell connected to an input port of the transmission gate logic cell;

generating a timing model associated with the transmission gate logic cell, wherein the timing model defines a delay from the input port to an output port of the transmission gate logic cell as a function of a driving strength of the sourcing cell; and

including the transmission gate logic cell and the associated timing model within a component cell library for use with an integrated circuit design tool,

wherein the steps of building, generating and including are steps that are performed by a computer.

17. The method of claim 16, wherein the defined delay represents a delay from a select port to a data output port of a combinatorial transmission gate logic cell.

18. The method of claim 16, wherein the defined delay represents a delay from a data input port to a data output port of a transmission gate-based flip-flop cell.

19. The method of claim 16, further comprising optimizing one of a structure of the transmission gate logic cell and the driving strength of the sourcing cell or both, to minimize state and load variances, prior to generating the timing model.

20. A non-transitory computer readable storage medium comprising a program of instructions which, when executed by a computer, perform the method steps of claim 16.