Satisfying routing rules during circuit design

• US 8,745,565 B2
• Filed: 10/29/2009
• Issued: 06/03/2014
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Gao, Tong
• Primary Examiner(s): Do, Thuan
• Assistant Examiner(s): Ngo, Brian
• Application Number:
  US12/608,470
• Publication Number:
  US 20110055786A1
• Time in Patent Office: 1,678 Days
• Field of Search: 716/50, 716/51, 716/55, 716/119, 716/126, 716/132, 716/110, 716/111, 716/134, 716/136
• US Class Current: 716/126
• CPC Class Codes: G06F 2117/06 Spare resources, e.g. for permanent fault suppression
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns effort levels to the set of routing rules, wherein a higher effort level for a routing rule indicates that a higher amount of resources are available to satisfy the routing rule. The system then modifies the routing solution to satisfy the routing rules based at least on the weights and the effort levels associated with the routing rules.

Claims

1. A method for satisfying routing rules during routing of an integrated circuit (IC) chip design, comprising:

receiving a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution;

assigning a weight to each routing rule in the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule;

assigning an effort level to each routing rule in the set of routing rules, wherein an effort level for a routing rule indicates one or more of;

the number of iterations that can be used to satisfy the routing rule, or the number of rip-up and reroutes that can be used to satisfy the routing rule; and

modifying, by computer, the routing solution to satisfy the routing rules based at least on the weights and the effort levels that were assigned to the routing rules.

2. The method of claim 1, wherein the set of routing rules include one or more hard routing rules and one or more soft routing rules, and assigning weights to the set of routing rules involves:

assigning a higher weight to a hard routing rule; and

assigning a lower weight to a soft routing rule.

3. The method of claim 2,

wherein the hard routing rules include foundry design rules;

and

wherein the soft routing rules include design for manufacturing (DFM) rules and user-defined rules.

4. The method of claim 1, wherein the set of effort levels comprise at least two different effort levels.

5. The method of claim 1, wherein a soft routing rule which is associated with a lower weight is not required to be satisfied during the routing of the IC chip design if not satisfying the soft routing rule causes a hard routing rule to be satisfied.

6. The method of claim 1, wherein the method further comprises determining an amount of time that a router can spend on satisfying a routing rule based at least on the routing rule'"'"'s effort-level.

7. The method of claim 1, wherein said modifying involves trying to minimize an aggregate weight of violated routing rules while spending computational time and resources in accordance with effort levels that are assigned to the routing rules.

8. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for satisfying routing rules during routing of an integrated circuit (IC) chip design, the method comprising:

receiving a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution;

assigning a weight to each routing rule in the set of routing rules by assigning one effort-level to each routing rule in the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule;

assigning an effort level to each routing rule in the set of routing rules, wherein an effort level for a routing rule indicates one or more of;

the number of iterations that can be used to satisfy the routing rule, or the number of rip-up and reroutes that can be used to satisfy the routing rule; and

modifying the routing solution to satisfy the routing rules based at least on the weights and the effort levels that were assigned to the routing rules.

9. The non-transitory computer-readable storage medium of claim 8, wherein the set of routing rules include one or more hard routing rules and one or more soft routing rules, and assigning weights to the set of routing rules involves:

assigning a higher weight to a hard routing rule; and

assigning a lower weight to a soft routing rule.

10. The non-transitory computer-readable storage medium of claim 9,

wherein the hard routing rules include foundry design rules;

and

wherein the soft routing rules include design for manufacturing (DFM) rules and user-defined rules.

11. The non-transitory computer-readable storage medium of claim 8, wherein the set of effort levels comprise at least two different effort levels.

12. The non-transitory computer-readable storage medium of claim 8, wherein a soft routing rule which is associated with a lower weight is not required to be satisfied during the routing of the IC chip design if not satisfying the soft routing rule causes a hard routing rule to be satisfied.

13. The non-transitory computer-readable storage medium of claim 8, wherein the method further comprises determining an amount time that a router can spend on satisfying a routing rule based at least on the routing rule'"'"'s effort-level.

14. The non-transitory computer-readable storage medium of claim 8, wherein said modifying involves trying to minimize an aggregate weight of violated routing rules while spending computational time and resources in accordance with effort levels that are assigned to the routing rules.

15. A system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design, comprising:

a receiving mechanism configured to receive a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution;

a assignment mechanism configured to assign a weight to each routing rule in the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule;

wherein the assignment mechanism is further configured to assign an effort level to each routing rule in the set of routing rules, wherein an effort level for a routing rule indicates one or more of;

the number of iterations that can be used to satisfy the routing rule, or the number of rip-up and reroutes that can be used to satisfy the routing rule; and

a modifying mechanism configured to modify the routing solution to satisfy the routing rules based at least on the weights and the effort levels that were assigned to the routing rules.

16. The system of claim 15, wherein the set of routing rules include one or more hard routing rules and one or more soft routing rules, and the assignment mechanism is configured to assign weights to the set of routing rules by:

assigning a higher weight to a hard routing rule; and

assigning a lower weight to a soft routing rule.

17. The system of claim 16,

wherein the hard routing rules include foundry design rules;

and

wherein the soft routing rules include design for manufacturing (DFM) rules and user-defined rules.

18. The system of claim 15, wherein the set of effort levels comprise at least two different effort levels.

19. The system of claim 15, wherein a soft routing rule which is associated with a lower weight is not required to be satisfied during the routing of the IC chip design if not satisfying the soft routing rule causes a hard routing rule to be satisfied.

20. The system of claim 15, wherein the system further comprises a determination mechanism configured to determine an amount time that a router can spend on satisfying a routing rule based at least on the routing rule'"'"'s effort-level.

21. The system of claim 15, wherein said modifying involves trying to minimize an aggregate weight of violated routing rules while spending computational time and resources in accordance with effort levels that are assigned to the routing rules.