Stacked oxide material, semiconductor device, and method for manufacturing the semiconductor device

• US 8,748,215 B2
• Filed: 11/22/2010
• Issued: 06/10/2014
• Est. Priority Date: 11/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US12/951,224
• Publication Number:
  US 20110127521A1
• Time in Patent Office: 1,296 Days
• Field of Search: 438/85, 438/104, 438149-151, 438/157, 438/159, 438/166, 438/482, 257/43, 257/52, 257/57, 257/59, 257/66
• US Class Current: 438/85
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02502 consisting of two layers
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 428/24174 : including sheet or component perpendicular to plane of web or sheet

Abstract

One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming an oxide component over a base component; forming a first oxide crystal component which grows from a surface toward an inside of the oxide component by heat treatment, and leaving an amorphous component just above a surface of the base component; and stacking a second oxide crystal component over the first oxide crystal component. In particular, the first oxide crystal component and the second oxide crystal component have common c-axes. Same-axis (axial) growth in the case of homo-crystal growth or hetero-crystal growth is caused.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer including a flat surface over a surface of a base;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer over the gate insulating layer;

causing crystal growth which proceeds from an upper surface toward an inside of the first oxide semiconductor layer by first heat treatment to form a first non-single crystalline layer;

forming a second oxide semiconductor layer over the first non-single crystalline layer;

causing crystal growth which proceeds from the first non-single crystalline layer toward an upper surface of the second oxide semiconductor layer over the first non-single crystalline layer by second heat treatment to form a second non-single crystalline layer; and

forming a source electrode layer and a drain electrode layer over a stack of the first non-single crystalline layer and the second non-single crystalline layer,

wherein a bottom interface whose crystal is aligned of the first non-single crystalline layer is provided to be spaced from a surface of the gate insulating layer.

2. The method for manufacturing a semiconductor device, according to claim 1,

wherein the first non-single crystalline layer is c-axis-aligned perpendicularly to a surface thereof.

3. The method for manufacturing a semiconductor device, according to claim 1,

wherein the second non-single crystalline layer is c-axis-aligned perpendicularly to a surface thereof.

4. The method for manufacturing a semiconductor device, according to claim 1, wherein the second oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer.

11. The method for manufacturing a semiconductor device, according to claim 1,

wherein the first oxide semiconductor layer is formed by a sputtering method using a first metal oxide target,

wherein the second oxide semiconductor layer is formed by a sputtering method using a second metal oxide target,

wherein each of the first metal oxide target and the second metal oxide target contains indium, gallium and zinc, and

wherein composition ratio of the first metal oxide target is different from the composition ratio of the second metal oxide target.

5. A semiconductor device comprising:

a gate electrode layer including a flat surface over a surface of a base;

a gate insulating layer over the gate electrode layer;

a metal oxide layer including an amorphous region over the gate insulating layer;

a first non-single crystalline layer which is c-axis-aligned perpendicularly to a surface, over the metal oxide layer including the amorphous region;

a second non-single crystalline layer which is on and in contact with the first non-single crystalline layer and c-axis-aligned perpendicularly to the surface thereof; and

a source electrode and a drain electrode over a stack of the first non-single crystalline layer and the second non-single crystalline layer,

wherein the first non-single crystalline layer and the second non-single crystalline layer are metal oxide layers.

6. The semiconductor device according to claim 5, wherein the second non-single crystalline layer has a larger thickness than the first non-single crystalline layer.

7. The semiconductor device according to claim 5, wherein the first non-single crystalline layer and the second non-single crystalline layer have a same electron affinity.

8. The semiconductor device according to claim 5, wherein the first non-single crystalline layer and the second non-single crystalline layer are formed using different materials.

9. The semiconductor device according to claim 5, wherein a difference in height at a region in the surface of the second non-single crystalline layer which overlaps with the gate electrode layer is less than or equal to 1 nm.

10. The semiconductor device according to claim 5, wherein a difference in height at a region in the surface of the second non-single crystalline layer which overlaps with the gate electrode layer is less than or equal to 0.2 nm.