Method of fabricating chip package

• US 8,748,227 B2
• Filed: 09/09/2008
• Issued: 06/10/2014
• Est. Priority Date: 03/30/2001
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Megit Acquisition Corp.
• Inventors: Lee, Jin-Yuan, Huang, Ching-Cheng, Lin, Mou-Shiung
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/206,754
• Publication Number:
  US 20090011542A1
• Time in Patent Office: 2,100 Days
• Field of Search: 438/106, 438/108, 438/614, 257/678, 257/778, 257/781, 257/E21.503, 257/E21.508, 257/E21.511, 257/E23.021, 257/738
• US Class Current: 438/108
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/293 Organic, e.g. plastic
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A Chip Scale Package (CSP) and a method of forming the same are disclosed. Single chips without the conventional ball mountings, are first attached to an adhesive-substrate (adsubstrate) composite having openings that correspond to the input/output (I/O) pads on the single chips to form a composite chip package. Ball mounting is then performed over the openings, thus connecting the I/O pads at the chip sites to the next level of packaging directly. In another embodiment, the adhesive layer is formed on the wafer side first to form an adwafer, which is then die sawed in CSPs. Then the CSPs with the adhesive already on them are bonded to a substrate. The composite chip package may optionally be encapsulated with a molding material. The CSPs provide integrated and shorter chip connections especially suited for high frequency circuit applications, and can leverage the currently existing test infrastructure.

Claims

1. A method of fabricating a chip package, comprising:

joining a top surface of a substrate and a bottom side of a die, wherein a first opening through said substrate is under said bottom side of said die, wherein said die comprises a first conductive layer, a second conductive layer and a passivation layer at said bottom side of said die, wherein a second opening in said passivation layer is under a first contact point of said first conductive layer, and said first contact point is at a top of said second opening, wherein said second conductive layer is coupled to said first contact point through said second opening, wherein said second conductive layer has a second contact point over said first opening;

after said joining said top surface of said substrate and said bottom side of said die, forming a conductive interconnect coupled to said second contact point though said first opening; and

after said joining said top surface of said substrate and said bottom side of said die, forming a molding material on a sidewall of said die and en-over said top surface of said substrate.

2. The method of claim 1, wherein said first conductive layer comprises copper.

3. The method of claim 1, wherein said first conductive layer comprises aluminum.

4. The method of claim 1, wherein said second conductive layer comprises nickel.

5. The method of claim 1, wherein said second conductive layer comprises copper.

6. The method of claim 1, after said forming said conductive interconnect and said forming said molding material, further comprising separating said molding material and said substrate into multiple portions, wherein said separating said molding material and said substrate comprises a sawing process.

7. The method of claim 1, wherein said molding material comprises an epoxy.

8. The method of claim 1 comprising said forming said molding material further over a top side of said die.

9. The method of claim 1, wherein said substrate comprises bismaleimide triazine.

10. A method of fabricating a chip package, comprising:

forming an adhesive material on a top surface of a substrate;

after said forming said adhesive material, joining said top surface of said substrate and a bottom side of a die with said adhesive material, wherein a first opening through said substrate is under said bottom side of said die, wherein said die comprises a copper layer, a conductive pad and a passivation layer at said bottom side of said die, wherein a second opening in said passivation layer is under a first contact point of said copper layer, and said first contact point is at a top of said second opening, wherein said conductive pad is coupled to said first contact point through said second opening, wherein said conductive pad has a second contact point over said first opening;

after said joining said top surface of said substrate and said bottom side of said die, forming a conductive interconnect coupled to said second contact point through said first opening;

after said joining said top surface of said substrate and said bottom side of said die, forming a molding material on a sidewall of said die and over said top surface of said substrate; and

after said forming said conductive interconnect and said forming said molding material, separating said molding material and said substrate into multiple portions, wherein said separating said molding material and said substrate comprises a sawing process.

11. The method of claim 10, wherein said conductive pad comprises nickel.

12. The method of claim 10, wherein said conductive pad comprises copper.

13. The method of claim 10, wherein said molding material comprises an epoxy.

14. The method of claim 10 comprising said forming said molding material further over a top side of said die.

15. The method of claim 10, wherein said substrate comprises bismaleimide triazine (BT).

16. A method of fabricating a chip package, comprising:

forming an adhesive material on a top surface of a substrate;

after said forming said adhesive material, joining said top surface of said substrate and a bottom side of a die with said adhesive material, wherein an opening through said substrate is under said bottom side of said die, wherein said die comprises a copper layer and a conductive pad at said bottom side of said die, wherein said conductive pad is coupled upwards to a bottom surface of said copper layer, wherein said conductive pad has a contact point over said opening;

after said joining said top surface of said substrate and said bottom side of said die, forming a conductive interconnect coupled to said contact point through said opening; and

after said joining said top surface of said substrate and said bottom side of said die, forming a molding material on a sidewall of said die and over said top surface of said substrate.

17. The method of claim 16, wherein said conductive pad comprises nickel.

18. The method of claim 16, wherein said conductive pad comprises copper.

19. The method of claim 16, wherein said molding material comprises an epoxy.

20. The method of claim 16 comprising said forming said molding material further over a top side of said die.

21. The method of claim 16, after said forming said conductive interconnect and said forming said molding material, further comprising separating said molding material and said substrate into multiple portions, wherein said separating said molding material and said substrate comprises a sawing process.

22. The method of claim 16, wherein said substrate comprises bismaleimide triazine.

23. A method of fabricating a chip package, comprising:

forming a molding material on a sidewall of a die and on a top side of said die, wherein said die comprises a conductive pad at a bottom side of said die and a passivation layer at said bottom side of said die, wherein an opening in said passivation layer is under a contact point of said conductive pad, and said contact point is at a top of said opening, wherein all of said passivation layer is vertically under an upper portion of said die, wherein said conductive pad comprises a copper layer;

after said forming said molding material, forming a conductive interconnect coupled to said conductive pad; and

after said forming said conductive interconnect, separating said molding material into multiple portions, wherein said separating said molding material comprises a sawing process.

24. The method of claim 23, wherein said molding material comprises an epoxy.

25. A method of fabricating a chip package, comprising:

joining a substrate and a die;

after said joining said substrate and said die, forming a molding material over said substrate and said die; and

after said forming said molding material, performing a sawing process to provide said chip package comprising a part of said substrate, said die over a top surface of said part of said substrate, a conductive bump having first portion located in an opening in said substrate and a second portion contacting said die, and a part of said molding material over said top surface and said die and at left and right sides of said die, wherein said part of said molding material has a left edge and a right edge substantially parallel with said left edge of said part of said molding material, wherein said part of said molding material comprises a first portion vertically over a left edge of said die, a second portion vertically over a right edge of said die and a third portion vertically over said die and between said first and second portions, wherein said first, second and third portions continuously extend over said die.

26. The method of claim 25, wherein said part of said substrate in said chip package comprises a ball-grid-array (BGA) substrate.

27. The method of claim 25, wherein said part of said substrate in said chip package has a left edge substantially aligned with said left edge of said part of said molding material and a right edge substantially aligned with said right edge of said part of said molding material.

28. The method of claim 25, wherein said die in said chip package comprises a copper pad at a bottom side of said die and vertically over said conductive bump.

29. The method of claim 25, wherein said die in said chip package comprises an aluminum-containing pad at a bottom side of said die and vertically over said conductive bump.

30. The method of claim 25, wherein said die in said chip package comprises a contact pad at a bottom side of said die, a passivation layer at said bottom side of said die, wherein an opening in said passivation layer is under a contact point of said contact pad, and said contact point is at a top of said opening, and a conductive layer at said bottom side of said die and under said passivation layer and said contact point, wherein said conductive layer is coupled to said contact point through said opening, wherein said conductive bump in said chip package is under said conductive layer.

31. The method of claim 30, wherein said conductive layer of said die in said chip package comprises copper.

32. The method of claim 30, wherein said conductive layer of said die in said chip package comprises nickel.

33. The method of claim 30, wherein said contact pad of said die in said chip package comprises copper.

34. The method of claim 30, wherein said contact pad of said die in said chip package comprises aluminum.

35. The method of claim 25, wherein said conductive bump in said chip package comprises tin.

36. The method of claim 25, wherein said conductive bump in said chip package comprises a tin-lead alloy.

37. The method of claim 25, wherein said conductive bump in said chip package comprises a tin-silver alloy.

38. The method of claim 25, wherein said conductive bump in said chip package comprises a solder ball.

39. The method of claim 25, wherein said part of said substrate in said chip package comprises bismaleimide triazine.

40. A method of fabricating a chip package, comprising:

joining a first substrate and a second substrate, wherein a first opening in said first substrate exposes a bottom side of said second substrate, wherein said second substrate comprises a copper pad and a separating layer at said bottom side of said second substrate, wherein a second opening in said separating layer is under a contact point of said copper pad, and said contact point is at a top of said second opening;

after said joining said first substrate and said second substrate, forming a conductive bump under said second substrate, the conductive bump having a first portion in said first opening, and a second portion conductive that is coupled to said contact point through said second opening; and

after said forming said conductive bump, performing a sawing process.

41. The method of claim 40, wherein said second substrate further comprises a conductive layer at said bottom side of said second substrate and under said separating layer and said contact point, wherein said conductive layer is coupled to said contact point through said second opening, wherein said first opening is under said conductive layer.

42. The method of claim 41, wherein said conductive layer comprises copper.

43. The method of claim 41, wherein said conductive layer comprises nickel.

44. The method of claim 40, wherein said first opening is vertically under said contact point.

45. The method of claim 40, wherein said conductive bump contacts a sidewall of said first opening.

46. The method of claim 40, wherein said second substrate comprises a die.

47. The method of claim 40 further comprising said joining said first substrate and said second substrate using an adhesive material.

48. A method of fabricating a chip package, comprising:

joining a first substrate and a second substrate comprising a die sawed from a wafer, wherein a first opening in said first substrate exposes a bottom side of said second substrate, wherein said second substrate comprises a contact pad and a separating layer at said bottom side of said second substrate, wherein a second opening in said separating layer is under a contact point of said contact pad, and said contact point is at a top of said second opening;

after said joining said first substrate and said second substrate, forming a conductive bump-under said second substrate, the conductive bump having a first portion in said first opening conductive that contacts a sidewall of said first opening, and a second portion conductive that is coupled to said contact point through said second opening; and

after said forming said conductive bump, performing a sawing process.

49. The method of claim 48, wherein said contact pad comprises a copper pad.

50. The method of claim 48, wherein said contact pad comprises aluminum.

51. The method of claim 48, wherein said second substrate further comprises a conductive layer at said bottom side of said second substrate and under said separating layer and said contact point, wherein said conductive layer is coupled to said contact point through said second opening, wherein said first opening is under said conductive layer.

52. The method of claim 51, wherein said conductive layer comprises copper.

53. The method of claim 51, wherein said metal conductive layer comprises nickel.

54. The method of claim 48, wherein said first opening is vertically under said contact point.

55. The method of claim 48 further comprising said joining said first substrate and said second substrate using an adhesive material.