Method of fabricating a gate

• US 8,748,239 B2
• Filed: 08/01/2013
• Issued: 06/10/2014
• Est. Priority Date: 11/04/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Jong-Pil, Jang, Young-Goan, Kim, Dong-Won, Cho, Hag-Ju
• Primary Examiner(s): GREEN, TELLY D
• Application Number:
  US13/956,482
• Publication Number:
  US 20130316514A1
• Time in Patent Office: 313 Days
• Field of Search: 438/142, 438/183, 438/195, 438/196, 438/176, 438/199, 257/411, 257/369
• US Class Current: 438/142
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method of fabricating a gate includes sequentially forming an insulation layer and a conductive layer on substantially an entire surface of a substrate. The substrate has a device isolation layer therein and a top surface of the device isolation layer is higher than a top surface of the substrate. The method includes planarizing a top surface of the conductive layer and forming a gate electrode by patterning the insulation layer and the conductive layer.

Claims

1. A method of fabricating a gate, the method comprising:

forming a device isolation layer in a substrate, a top surface of the device isolation layer being higher than a top surface of the substrate;

sequentially forming a first layer and a second layer on substantially an entirety of the substrate including the device isolation layer, the second layer having a stepped surface on the substrate, the stepped surface overlapping the device isolation layer;

planarizing the second layer such that the stepped surface is removed; and

forming a plurality of stacked structures spaced apart on the substrate, after planarizing the second layer by patterning the first layer and the second layer to form a plurality of patterned first layers and a plurality of patterned second layers, at least one of the plurality of patterned second layers being on the device isolation layer, a top surface of each of the plurality of patterned second layers being arranged at a same distance from the substrate.

2. The method as claimed in claim 1, wherein the at least one of the plurality of patterned second layers on the device isolation layer has a height that is less than a height of another of the plurality of patterned second layers spaced apart from the device isolation layer.