Method of manufacturing semiconductor device, and semiconductor device

• US 8,748,261 B2
• Filed: 10/26/2011
• Issued: 06/10/2014
• Est. Priority Date: 04/23/2009
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Takehara, Kei
• Primary Examiner(s): Ahmadi, Mohsen
• Application Number:
  US13/317,697
• Publication Number:
  US 20120043603A1
• Time in Patent Office: 958 Days
• US Class Current: 438/259
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes a first-conductivity-type semiconductor layer, a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer, first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another, a source interconnect layer buried in the first through third trenches, the source interconnect layer including a protruding portion, a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer, a source metal contacting the protruding portion of the source interconnect layer, and a gate metal contacting the gate electrode in the third trench. A contact face between the source metal and the protruding portion at the second trench is formed higher than a contact face between the gate metal and the gate electrode at the third trench.

Claims

1. A semiconductor device, comprising:

a first-conductivity-type semiconductor layer;

a base region of a second-conductivity-type formed in an upper portion of the first-conductivity-type semiconductor layer;

first though third trenches penetrating through the base region and reaching to the first-conductivity-type semiconductor layer, the first through third trenches being linked to one another;

a source interconnect layer buried in the first through third trenches, the source interconnect layer comprising a protruding portion protruding from an upper end of the second trench;

a gate electrode buried in the first trench and the third trench, and formed over the source interconnect layer;

a source metal contacting the protruding portion of the source interconnect layer; and

a gate metal contacting the gate electrode in the third trench,

wherein a contact face between the source metal and the protruding portion at the second trench is higher than a contact face between the gate metal and the gate electrode at the third trench.

2. The semiconductor device according claim 1, further comprising a gate interconnect layer formed at a sidewall of the protruding portion of the source interconnect layer,

wherein the gate electrode and the gate interconnect layer form a solid line.

3. The method according to claim 2, wherein the source interconnect layer comprises a first polysilicon layer, and

wherein the gate electrode and the gate interconnect layer comprise a second polysilicon layer.

4. The semiconductor device, according to claim 1, wherein the gate electrode formed in the first trench is covered by an interlayer insulating film, and the source metal is formed over the interlayer insulating film.

5. The semiconductor device according to claim 1, wherein a width of the third trench is larger than a width of the first trench, and larger than a width of the second trench.

6. The semiconductor device according to claim 1, further comprising a source region of the first-conductivity-type formed in an upper portion of the base region,

wherein both the source region and the base region contact the source metal.

7. The semiconductor device according to claim 6, wherein an upper surface of the gate electrode buried in the first trench is lower than an upper surface of the source region.

8. The semiconductor device according to claim 1, wherein an upper surface of the source interconnect layer buried in the first and third trenches is lower than the base region.

9. The semiconductor device according to claim 1, wherein the first-conductivity-type semiconductor layer comprises:

a cell region in which MOS transistor structure is provided; and

a terminal region formed outside the cell region,

wherein the first trench is formed in the cell region, and

wherein the second and third trenches are formed in the terminal region.

10. The semiconductor device according to claim 9, wherein the third trench is formed outwardly of the second trench.