Method of making MOSFET integrated with schottky diode with simplified one-time top-contact trench etching
First Claim
1. A method for fabricating a MOSFET integrated with Schottky diode (MOSFET/SKY), expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising:
- a) forming, in an epitaxial layer overlaying a semiconductor substrate, a gate trench and depositing gate material therein;
b) forming a body region in the epitaxial layer, a source region atop the body region and a dielectric region atop the gate trench and the source region;
c) etching a top contact trench (TCT) with vertical side walls defining a Schottky diode cross-sectional width SDCW;
c1) through the dielectric region and the source region thus defining a source-contact depth (SCD); and
c2) partially into the body region by a predetermined total body-contact depth (TBCD);
d) creating;
d1) into the side walls of the TCT and beneath the SCD, a heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<
TBCD; and
d2) into a sub-contact trench zone (SCTZ) beneath the floor of the TCT, an embedded Shannon implant region (ESIR); and
e) forming a metal layer;
e1) in contact with the ESIR, the body region and the source region; and
e2) filling the TCT and covering the dielectric regionwhereby completing the MOSFET/SKY with only one-time etching of its TCT.
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Abstract
Method for fabricating MOSFET integrated with Schottky diode (MOSFET/SKY) is disclosed. Gate trench is formed in an epitaxial layer overlaying semiconductor substrate, gate material is deposited therein. Body, source, dielectric regions are successively formed upon epitaxial layer and the gate trench. Top contact trench (TCT) is etched with vertical side walls defining Schottky diode cross-sectional width SDCW through dielectric and source region defining source-contact depth (SCD); and partially into body region by total body-contact depth (TBCD). A heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<TBCD is created into side walls of TCT and beneath SCD. An embedded Shannon implant region (ESIR) is created into sub-contact trench zone (SCTZ) beneath TCT floor. A metal layer is formed in contact with ESIR, body and source region. The metal layer also fills TCT and covers dielectric region thus completing the MOSFET/SKY with only one-time etching of its TCT.
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Citations
8 Claims
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1. A method for fabricating a MOSFET integrated with Schottky diode (MOSFET/SKY), expressed in an X-Y-Z Cartesian coordinate system with the X-Y plane parallel to its major semiconductor chip plane, comprising:
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a) forming, in an epitaxial layer overlaying a semiconductor substrate, a gate trench and depositing gate material therein; b) forming a body region in the epitaxial layer, a source region atop the body region and a dielectric region atop the gate trench and the source region; c) etching a top contact trench (TCT) with vertical side walls defining a Schottky diode cross-sectional width SDCW; c1) through the dielectric region and the source region thus defining a source-contact depth (SCD); and c2) partially into the body region by a predetermined total body-contact depth (TBCD); d) creating; d1) into the side walls of the TCT and beneath the SCD, a heavily-doped embedded body implant region (EBIR) of body-contact depth (BCD)<
TBCD; andd2) into a sub-contact trench zone (SCTZ) beneath the floor of the TCT, an embedded Shannon implant region (ESIR); and e) forming a metal layer; e1) in contact with the ESIR, the body region and the source region; and e2) filling the TCT and covering the dielectric region whereby completing the MOSFET/SKY with only one-time etching of its TCT. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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Specification