Process for manufacturing an improved analog transistor

• US 8,748,270 B1
• Filed: 07/20/2012
• Issued: 06/10/2014
• Est. Priority Date: 03/30/2011
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Thompson, Scott E., Gregory, Paul E.
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/553,902
• Time in Patent Office: 690 Days
• Field of Search: 438/275, 438/279, 257/E21.443
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

An analog transistor useful for low noise applications or for electrical circuits benefiting from tight control of threshold voltages and electrical characteristics is described. The analog transistor includes a substantially undoped channel positioned under a gate dielectric between a source and a drain with the undoped channel not being subjected to contaminating threshold voltage implants or halo implants. The channel is supported on a screen layer doped to have an average dopant density at least five times as great as the average dopant density of the substantially undoped channel which, in turn, is supported by a doped well having an average dopant density at least twice the average dopant density of the substantially undoped channel.

Claims

1. A process for manufacturing an analog transistor comprising:

providing a doped well;

forming a screen layer that contacts and overlies at least a portion of the doped well;

forming an epitaxial undoped channel layer above the screen layer, and the undoped channel not being subjected to contaminating threshold voltage implants or halo implants;

forming a dopant migration resistant layer above the screen layer;

forming a gate dielectric and gate electrode above the undoped channel and positioned between a source and a drain, the source and drain configured to respond to an analog signal; and

maintaining process conditions so that a portion of the undoped channel adjacent to the gate dielectric remains undoped in the final analog transistor.

2. The process of claim 1, further comprising the step of forming a threshold voltage setting layer positioned between the undoped channel and the screen layer, the threshold voltage setting layer extending at least partially between the source and the drain.

3. The process of claim 2, further comprising the step of counter doping the threshold voltage setting layer with respect to the screen layer.

4. The process of claim 2, further comprising the step of forming an asymmetric threshold voltage setting layer that extends only partially between the source and the drain.

5. The process of claim 2, wherein the threshold voltage setting layer is formed by out diffusion from the screen layer into an epitaxially grown layer.

6. The process of claim 2, wherein the threshold voltage setting layer is formed by growing an epitaxial layer on the screen layer and doping the epitaxial layer through either implantation or in-situ doping.

7. The process of claim 2, wherein the threshold voltage setting layer is formed by delta doping to form an offset doped plane.

8. The process of claim 2, wherein the threshold voltage setting layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.

9. The process of claim 2, further comprising:

forming a dopant migration resistant layer above the threshold voltage setting layer.

11. The process of claim 1, wherein the gate electrode is formed by depositing a gate metal, wherein the gate metal is selected to have a work function intermediate between band edge and midgap.

12. The process of claim 1, further comprising the step of forming an electrical tap to the doped well to permit biasing that adjusts threshold voltage.

13. The process of claim 1, wherein the screen layer is formed as part of a blanket layer underlying a plurality of gate dielectrics and gate electrodes.

14. The process of claim 1, wherein the screen layer is formed by epitaxial growth subject to at least one of implantation and in situ doping.

15. The process of claim 1, wherein the screen layer is positioned above the bottom of the source and drain.

10. The process of claim further comprising the steps of:

forming a first channel LDD extending from the source toward the drain for a first distance; and

forming a second channel LDD extending from the drain toward the source for a second distance selected to be less than the first distance.

16. A process for manufacturing an analog transistor comprising:

providing a doped well;

forming a screen layer that contacts and overlies at least a portion of the doped well;

forming an epitaxial undoped channel layer above the screen layer, and the undoped channel not being subjected to contaminating threshold voltage implants or halo implants;

forming a threshold voltage setting layer positioned between the undoped channel and the screen layer, the threshold voltage setting layer extending at least partially between a source and a drain;

forming a gate dielectric and gate electrode above the undoped channel and positioned between the source and the drain, the source and drain configured to respond to an analog signal;

forming an electrical tap to the doped well to permit biasing that adjusts threshold voltage;

maintaining process conditions so that a portion of the undoped channel adjacent to the gate dielectric remains undoped in the final analog transistor.

17. The process of claim 16, further comprising counter doping the threshold voltage setting layer with respect to the screen layer.

18. The process of claim 16, wherein the gate electrode is formed by depositing a gate metal, wherein the gate metal is selected to have a work function intermediate between band edge and midgap.

19. The process of claim 16, further comprising:

forming a first dopant migration resistant layer above the threshold voltage setting layer;

forming a second dopant migration resistant layer above the threshold voltage setting layer.