Non-volatile memory arrays comprising rail stacks with a shared diode component portion for diodes of electrically isolated pillars

• US 8,748,859 B2
• Filed: 04/06/2012
• Issued: 06/10/2014
• Est. Priority Date: 06/13/2008
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Hsia, Kang-Jay, Petti, Christopher J, Li, Calvin K
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): HALL, VICTORIA KATHLEEN
• Application Number:
  US13/441,805
• Publication Number:
  US 20120187361A1
• Time in Patent Office: 795 Days
• Field of Search: 257/2, 257/5, 257/50, 257/E47.001, 257/E21.004, 365/148, 438/382
• US Class Current: 257/2
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes

Abstract

An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. Two-terminal devices such as passive element memory cells can include a diode steering element in series with an antifuse and/or other state change element. The devices are formed using pillar structures at the intersections of upper and lower sets of conductors. The height of the pillar structures are reduced by forming part of the diode for each pillar in a rail stack with one of the conductors. A diode in one embodiment can include a first diode component of a first conductivity type and a second diode component of a second conductivity type. A portion of one of the diode components is divided into first and second portions with one on the portions being formed in the rail stack where it is shared with other diodes formed using pillars at the rail stack.

Claims

1. A non-volatile semiconductor memory, comprising:

a substrate;

a plurality of substantially parallel and substantially coplanar first conductors at a first height above the substrate, the first conductors elongated in a first direction;

a plurality of substantially parallel and substantially coplanar rail stacks at a second height above the substrate, the rail stacks elongated in a second direction substantially orthogonal to the first direction, each rail stack including a second conductor and a first portion of a first diode component for a plurality of diodes associated with the rail stack; and

a plurality of pillars formed between intersections of the plurality of first conductors and the plurality of rail stacks, the plurality of pillars including a first set of pillars formed at the intersection of a first rail stack and the plurality of first conductors, the first set of pillars each including a second portion of the first diode component for the plurality of diodes associated with the first rail stack, a second diode component and a state change element, the second diode component comprising heavily doped polysilicon of a first conductivity type, the first portion of the first diode component and the second portion of the first diode component comprising lightly doped polysilicon of a second conductivity type that is opposite to the first conductivity type.

2. A non-volatile semiconductor memory according to claim 1, wherein the plurality of rail stacks is a second plurality of rail stacks, the semiconductor memory further comprising:

a first plurality of substantially parallel and substantially coplanar rail stacks at the second height above the substrate, the first plurality of rail stacks including the plurality of first conductors.

3. A non-volatile semiconductor memory according to claim 1, wherein the state change element comprises a resistivity change material.

4. A method of fabricating an integrated circuit device, comprising:

forming a plurality of substantially parallel and substantially coplanar first conductors at a first height above a substrate, the first conductors elongated in a first direction;

forming a plurality of substantially parallel and substantially coplanar rail stacks at a second height above the substrate, the rail stacks elongated in a second direction substantially orthogonal to the first direction, each rail stack including a second conductor and a first portion of a first diode component for a plurality of diodes associated with the rail stack; and

forming a plurality of pillars between intersections of the plurality of first conductors and the plurality of rail stacks, the plurality of pillars including a first set of pillars formed at the intersection of a first rail stack and the plurality of first conductors, the first set of pillars each including a second portion of the first diode component for the plurality of diodes associated with the first rail stack, a second diode component and a state change element, the second diode component comprising heavily doped polysilicon of a first conductivity type, the first portion of the first diode component and the second portion of the first diode component comprising intrinsic polysilicon.

5. The method of claim 4, wherein:

the plurality of first conductors, the second conductors, the first diode components, the second diode components and the state change elements form a plurality of non-volatile memory cells;

the integrated circuit device includes a monolithic three-dimensional non-volatile memory array;

the plurality of non-volatile memory cells are formed at a first memory level of the monolithic three-dimensional non-volatile memory array; and

the integrated circuit device includes at least one additional memory level.

6. The method of claim 4, wherein:

the first height above the substrate is higher than the second height above the substrate.

7. The method of claim 6, wherein forming the plurality of substantially parallel and substantially coplanar first conductors and forming the plurality of pillars includes:

forming a first conducting layer over the substrate;

forming a heavily doped polysilicon layer over the first conducting layer;

forming an antifuse layer over the heavily doped polysilicon layer;

forming a first intrinsic polysilicon layer over the antifuse layer;

applying a first pattern over the first intrinsic polysilicon layer; and

etching the first conducting layer, the heavily doped polysilicon layer, the antifuse layer, and the first intrinsic polysilicon layer in accordance with the first pattern, wherein patterning and etching forms strips of each layer that are elongated in the first direction, the strips including the plurality of first conductors.

8. The method of claim 7, wherein forming the plurality of substantially parallel and substantially coplanar rail stacks at the second height above the substrate includes:

forming a second intrinsic polysilicon layer over the first intrinsic polysilicon layer after patterning and etching;

forming a second conducting layer over the second intrinsic polysilicon layer;

applying a second pattern over the second conducting layer; and

etching the second conducting layer and the second intrinsic polysilicon layer in accordance with the second pattern to form the plurality of rail stacks, the second intrinsic polysilicon layer forming the first portion of the first diode component for each rail stack and the second conducting layer forming the second conductor for each rail stack.

9. The method of claim 8, wherein forming the plurality of pillars further includes:

etching the first intrinsic polysilicon layer, the antifuse layer and the heavily doped polysilicon layer in accordance with the second pattern to form the plurality of pillars.

10. A non-volatile semiconductor memory, comprising:

a substrate;

a plurality of substantially parallel and substantially coplanar first conductors at a first height above the substrate, the first conductors elongated in a first direction;

a plurality of substantially parallel and substantially coplanar rail stacks at a second height above the substrate, the rail stacks elongated in a second direction substantially orthogonal to the first direction, each rail stack including a second conductor and a first portion of a first diode component for a plurality of diodes associated with the rail stack; and

a plurality of pillars formed between intersections of the plurality of first conductors and the plurality of rail stacks, the plurality of pillars including a first set of pillars formed at the intersection of a first rail stack and the plurality of first conductors, the first set of pillars each including a second portion of the first diode component for the plurality of diodes associated with the first rail stack, a second diode component and a state change element, the second diode component comprising heavily doped polysilicon of a first conductivity type, the first portion of the first diode component and the second portion of the first diode component comprising intrinsic polysilicon.

11. A non-volatile semiconductor memory according to claim 10, wherein:

the plurality of first conductors, the second conductors, the first diode components, the second diode components and the state change elements form a plurality of non-volatile memory cells;

the non-volatile semiconductor memory includes a monolithic three-dimensional non-volatile memory array;

the plurality of non-volatile memory cells are formed at a first memory level of the monolithic three-dimensional non-volatile memory array; and

the non-volatile semiconductor memory includes at least one additional memory level.

12. A non-volatile semiconductor memory according to claim 10, wherein:

the first height above the substrate is higher than the second height above the substrate.

13. A method of fabricating an integrated circuit device, comprising:

forming a plurality of substantially parallel and substantially coplanar first conductors at a first height above a substrate, the first conductors elongated in a first direction;

forming a plurality of substantially parallel and substantially coplanar rail stacks at a second height above the substrate, the rail stacks elongated in a second direction substantially orthogonal to the first direction, each rail stack including a second conductor and a first portion of a first diode component for a plurality of diodes associated with the rail stack; and

forming a plurality of pillars between intersections of the plurality of first conductors and the plurality of rail stacks, the plurality of pillars including a first set of pillars formed at the intersection of a first rail stack and the plurality of first conductors, the first set of pillars each including a second portion of the first diode component for the plurality of diodes associated with the first rail stack, a second diode component and a state change element, the second diode component comprising heavily doped polysilicon of a first conductivity type, the first portion of the first diode component and the second portion of the first diode component comprising lightly doped polysilicon of a second conductivity type that is opposite to the first conductivity type.

14. The method of claim 13, wherein:

the plurality of first conductors, the second conductors, the first diode components, the second diode components and the state change elements form a plurality of non-volatile memory cells;

the integrated circuit device includes a monolithic three-dimensional non-volatile memory array;

the plurality of non-volatile memory cells are formed at a first memory level of the monolithic three-dimensional non-volatile memory array; and

the integrated circuit device includes at least one additional memory level.

15. The method of claim 13, wherein:

the first height above the substrate is higher than the second height above the substrate.

16. The method of claim 15, wherein forming the plurality of substantially parallel and substantially coplanar first conductors and forming the plurality of pillars includes:

forming a first conducting layer over the substrate;

forming a heavily doped polysilicon layer over the first conducting layer;

forming an antifuse layer over the heavily doped polysilicon layer;

forming a first intrinsic polysilicon layer over the antifuse layer;

applying a first pattern over the first intrinsic polysilicon layer; and

etching the first conducting layer, the heavily doped polysilicon layer, the antifuse layer, and the first intrinsic polysilicon layer in accordance with the first pattern, wherein patterning and etching forms strips of each layer that are elongated in the first direction, the strips including the plurality of first conductors.

17. The method of claim 16, wherein forming the plurality of substantially parallel and substantially coplanar rail stacks at the second height above the substrate includes:

forming a second intrinsic polysilicon layer over the first intrinsic polysilicon layer after patterning and etching;

forming a second conducting layer over the second intrinsic polysilicon layer;

applying a second pattern over the second conducting layer; and

etching the second conducting layer and the second intrinsic polysilicon layer in accordance with the second pattern to form the plurality of rail stacks, the second intrinsic polysilicon layer forming the first portion of the first diode component for each rail stack and the second conducting layer forming the second conductor for each rail stack.

18. The method of claim 17, wherein forming the plurality of pillars further includes:

etching the first intrinsic polysilicon layer, the antifuse layer and the heavily doped polysilicon layer in accordance with the second pattern to form the plurality of pillars.