Thin film transistor, method of manufacturing the same, and display device

• US 8,748,878 B2
• Filed: 02/22/2010
• Issued: 06/10/2014
• Est. Priority Date: 03/04/2009
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yamaguchi, Norihiko, Taniguchi, Satoshi, Miyashita, Hiroko, Terai, Yasuhiro
• Primary Examiner(s): Malsawma, Lex
• Assistant Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US12/709,805
• Publication Number:
  US 20100224871A1
• Time in Patent Office: 1,569 Days
• Field of Search: 257/43, 257/59, 257/61, 257/408, 257/E29.296, 257/E21.46, 438/104
• US Class Current: 257/41
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

The present application provides a thin film transistor and a method of manufacturing same capable of suppressing diffusion of aluminum to oxide semiconductor and selectively etching oxide semiconductor and aluminum oxide. The thin film transistor includes: a gate electrode; a channel layer whose main component is oxide semiconductor; a gate insulating film provided between the gate electrode and the channel layer; a sealing layer provided on the side opposite to the gate electrode, of the channel layer; and a pair of electrodes which are in contact with the channel layer and serve as a source and a drain. The sealing layer includes at least a first insulating film made of a first insulating material, and a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer.

Claims

1. A thin film transistor comprising:

a gate electrode;

a channel layer whose main component is oxide semiconductor;

a gate insulating film provided between the gate electrode and the channel layer;

a sealing layer provided on the side opposite to the gate electrode, of the channel layer;

a pair of electrodes formed over a portion of the sealing layer and over a portion of the gate electrode which are in contact with the channel layer and serve as a source and a drain; and

a channel protection film formed on the sealing layer such that the sealing layer is formed between the channel layer and the channel protection film,

wherein the sealing layer includes at least

a first insulating film made of a first insulating material, and

a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer, and

wherein the first insulating material is selected from the group consisting of Al₂O₃, Ga₂O₃ and ZrO₂ and the second insulating material is at least one of SiO_X, SiN_X, Y₂O₃, TaO, HfO and oxynitrides thereof,

wherein the first insulating layer and the second insulating layer are etched during a single photolithographic process, and

wherein the channel protection film is formed on the sealing layer only in areas corresponding to the gate electrode.

2. The thin film transistor according to claim 1, wherein the oxide semiconductor is at least one of ZnO, ITO, and In-M-Zn—

O where M is at least one of Ga, Al, Fe, and Sn.

3. The thin film transistor according to claim 1, wherein the gate electrode, the gate insulating film, the channel layer, and the sealing layer are provided in this order on a substrate.

4. The thin film transistor according to claim 1, wherein thickness of the first insulating film is 10 nm to 500 nm both inclusive.

5. The thin film transistor according to claim 1, wherein the second insulating material is SiO_x.

6. The thin film transistor according to claim 1, wherein the first insulating film suppresses desorption of oxygen from the channel layer.

7. The thin film transistor according to claim 1, wherein the second insulating film prevents diffusion of Al from the first insulating film into the channel layer.

8. The thin film transistor according to claim 1, wherein the pair of electrodes are formed in regions extending from a surface of the channel protection film to the surface of the channel layer via side faces of the sealing layer.

9. The thin film transistor according to claim 1, wherein a protection film is formed over the pair of electrodes and over an exposed portion of the channel protection film between the pair of electrodes.

10. The thin film transistor according to claim 1, wherein the first insulating film has etching selectivity to the channel protection film.

11. The thin film transistor according to claim 1, wherein the etching selectivity between the first insulating film and the second insulating film is configured such that the second insulating film is an etching stop layer for the first insulating film.

12. The thin film transistor according to claim 11, wherein the etching selectivity between the second insulating film and the channel layer is configured such that the channel layer is an etching stop layer for the second insulating film.

13. The thin film transistor according to claim 12, wherein the first insulating film is dry etched with a first etching gas, and the second insulating film is dry etched with a second etching gas that is different from the first etching gas.

14. The thin film transistor according to claim 1, wherein the etching selectivity between the first insulating film and the second insulating film is configured such that the second insulating film is an etching stop layer for the first insulating film.

15. The thin film transistor according to claim 14, wherein the etching selectivity between the second insulating film and the channel layer is configured such that the channel layer is an etching stop layer for the second insulating film.

16. The thin film transistor according to claim 15, wherein the first insulating film is dry etched with a first etching gas, and the second insulating film is dry etched with a second etching gas that is different from the first etching gas.

17. The thin film transistor according to claim 1, wherein the gate electrode has a two-layer structure including a molybdenum layer and an aluminum layer or an aluminum alloy layer.

18. The thin film transistor according to claim 17, wherein the aluminum alloy layer is an aluminum-neodymium alloy layer.

19. The thin film transistor according to claim 1, wherein the channel layer includes a conductive oxide semiconductor selected from the group consisting of zinc oxide (ZnO), Indium Tin Oxide (ITO), and In-M-Zn—

O (M is at least one of Ga, Al, Fe, and Sn).

20. The thin film transistor according to claim 1, wherein a film thickness of the sealing layer ranges from 50 nm to 300 nm.

21. The thin film transistor according to claim 1, wherein the first insulating material is Ga₂O₃.

22. The thin film transistor according to claim 1, wherein the first insulating material is ZrO₂.

23. A display device comprising a thin film transistor and a display element, wherein the thin film transistor includes:

a gate electrode;

a channel layer whose main component is oxide semiconductor;

a gate insulating film provided between the gate electrode and the channel layer;

a sealing layer provided on the side opposite to the gate electrode, of the channel layer;

a pair of electrodes formed over a portion of the sealing layer and over a portion of the gate electrode which are in contact with the channel layer and serve as a source and a drain; and

a channel protection film formed on the sealing layer such that the sealing layer is formed between the channel layer and the channel protection film, and

the sealing layer includes at least

a first insulating film made of a first insulating material; and

a second insulating film made of a second insulting material having etching selectivity to each of the oxide semiconductor and the first insulating material and provided between the first insulating film and the channel layer,

wherein the first insulating material is selected from the group consisting of Al₂O₃, Ga₂O₃ and ZrO₂ and the second insulating material is at least one of SiO_X, SiN_X, Y₂O₃, TaO, HfO and oxynitrides thereof,

wherein the first insulating layer and the second insulating layer are etched during a single photolithographic process, and

wherein the channel protection film is formed on the sealing layer only in areas corresponding to the gate electrode.

24. The display device according to claim 23, wherein the etching selectivity between the first insulating film and the second insulating film is configured such that the second insulating film is an etching stop layer for the first insulating film.

25. The display device according to claim 24, wherein the etching selectivity between the second insulating film and the channel layer is configured such that the channel layer is an etching stop layer for the second insulating film.

26. The display device according to claim 25, wherein the first insulating film is dry etched with a first etching gas, and the second insulating film is dry etched with a second etching gas that is different from the first etching gas.

27. The display device according to claim 23, wherein the gate electrode has a two-layer structure including a molybdenum layer and an aluminum layer or an aluminum alloy layer.

28. The display device according to claim 27, wherein the aluminum alloy layer is an aluminum-neodymium alloy layer.

29. The display device according to claim 23, wherein the channel layer includes a conductive oxide semiconductor selected from the group consisting of zinc oxide (ZnO), Indium Tin Oxide (ITO), and In-M-Zn—

O (M is at least one of Ga, Al, Fe, and Sn).

30. The display device according to claim 23, wherein a film thickness of the sealing layer ranges from 50 nm to 300 nm.

31. The display device according to claim 23, wherein the first insulating material is Ga₂O₃.

32. The display device according to claim 23, wherein the first insulating material is ZrO₂.