Semiconductor device

• US 8,748,881 B2
• Filed: 11/22/2010
• Issued: 06/10/2014
• Est. Priority Date: 11/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US12/951,249
• Publication Number:
  US 20110127523A1
• Time in Patent Office: 1,296 Days
• Field of Search: 257/43, 257/E29.296, 257/E21.476, 438/104
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/2206 Amorphous materials
• CPC Class Codes: H01L 29/221 including two or more compounds , e.g. alloys H01L29/2206 takes precedence
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Claims

1. A semiconductor device comprising:

a first oxide semiconductor layer comprising a first crystalline region over a substrate having an insulating surface;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer each being in contact with the second oxide semiconductor layer;

a first gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and

a first gate electrode layer over the second oxide semiconductor layer with the first gate insulating layer interposed therebetween,

wherein the second oxide semiconductor layer comprises a second crystalline region having a c-axis alignment same or substantially same as that of the first crystalline region,

wherein the c-axis of the second crystalline region is aligned in a direction within ±

10°

from a perpendicular direction to a surface of the second oxide semiconductor layer, and

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, zinc and a metal other than indium and zinc.

2. The semiconductor device according to claim 1, further comprising:

a second gate electrode layer over the substrate having the insulating surface;

a second gate insulating layer over the first gate electrode layer,

wherein the first oxide semiconductor layer is located over the second gate insulating layer.

3. The semiconductor device according to claim 1, wherein a variation in height of the surface of the second oxide semiconductor layer is 1 nm or less in a region between the source electrode layer and the drain electrode layer.

4. The semiconductor device according to claim 1, wherein the substrate having the insulating surface includes an oxide or a nitride.

5. The semiconductor device according to claim 1, wherein the first crystalline region included in the first oxide semiconductor layer has an average thickness greater than or equal to 2 nm and less than or equal to 10 nm.

6. The semiconductor device according to claim 1, wherein the metal comprises gallium.

7. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer or the second oxide semiconductor layer is a purified oxide semiconductor layer.

8. The semiconductor device according to claim 1, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a carrier density lower than 1.0×

10¹² cm<sup>−

3</sup>.

9. The semiconductor device according to claim 1, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a hydrogen concentration lower than 5×

10¹⁹ cm<sup>−

3</sup>.

10. The semiconductor device according to claim 1, wherein the sum of thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 3 nm and less than or equal to 50 nm.

11. The semiconductor device according to claim 1, wherein the first crystalline region of the first oxide semiconductor layer has the same electron affinity as a crystal comprised in the second oxide semiconductor layer.

12. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer has a depression portion.

13. The semiconductor device according to claim 1, wherein the second oxide semiconductor layer includes a high-purity crystalline region.

14. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include materials including the same main component.

15. The semiconductor device according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include different materials.

16. The semiconductor device according to claim 1, wherein insulating layers having substantially the same shape as the source electrode layer and the drain electrode layer are included over the source electrode layer and the drain electrode layer.

17. The semiconductor device according to claim 1, wherein portions in contact with the second oxide semiconductor layer of the source electrode layer and the drain electrode layer include a material having a low oxygen affinity.

18. A semiconductor device comprising:

a gate electrode layer over a substrate having an insulating surface;

a gate insulating layer over the gate electrode layer;

a first oxide semiconductor layer over the gate electrode layer with the gate insulating layer therebetween;

a second oxide semiconductor layer over the first oxide semiconductor layer; and

a source electrode layer and a drain electrode layer each being in contact with the second oxide semiconductor layer,

wherein the first oxide semiconductor layer comprises a first crystalline region,

wherein the second oxide semiconductor layer comprises a second crystalline region having a c-axis alignment same or substantially same as that of the first crystalline region,

wherein the c-axis of the second crystalline region is aligned in a direction within ±

10°

from a perpendicular direction to a surface of the second oxide semiconductor layer, and

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, zinc and a metal other than indium and zinc.

19. The semiconductor device according to claim 18, further comprising an insulating layer over the source electrode layer, the drain electrode layer and the second oxide semiconductor layer,

wherein the insulating layer is in contact with part of the surface of the second oxide semiconductor layer.

20. The semiconductor device according to claim 18, wherein a variation in height of the surface of the second oxide semiconductor layer is 1 nm or less in a region between the source electrode layer and the drain electrode layer.

21. The semiconductor device according to claim 18, wherein the first crystalline region included in the first oxide semiconductor layer has an average thickness greater than or equal to 2 nm and less than or equal to 10 nm.

22. The semiconductor device according to claim 18, wherein the metal comprises gallium.

23. The semiconductor device according to claim 18, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a carrier density lower than 1.0×

10¹² cm<sup>−

3</sup>.

24. The semiconductor device according to claim 18, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a hydrogen concentration lower than 5×

10¹⁹ cm<sup>−

3</sup>.

25. The semiconductor device according to claim 18, wherein a sum of thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 3 nm and less than or equal to 50 nm.

26. The semiconductor device according to claim 18, wherein the first crystalline region of the first oxide semiconductor layer has the same electron affinity as a crystal comprised in the second oxide semiconductor layer.

27. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include materials including the same main component.

28. The semiconductor device according to claim 18, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include different materials.

29. The semiconductor device according to claim 18, wherein portions in contact with the second oxide semiconductor layer of the source electrode layer and the drain electrode layer include a material having a low oxygen affinity.

30. A semiconductor device comprising:

a first gate electrode layer over a substrate having an insulating surface;

a first gate insulating layer over the first gate electrode layer;

a first oxide semiconductor layer over the first gate electrode layer with the first gate insulating layer therebetween;

a second oxide semiconductor layer over the first oxide semiconductor layer;

a source electrode layer and a drain electrode layer each being electrically connected to the second oxide semiconductor layer;

a second gate insulating layer over the second oxide semiconductor layer; and

a second gate electrode layer over the second oxide semiconductor layer with the second gate insulating layer interposed therebetween,

wherein the first oxide semiconductor layer comprises a first crystalline region,

wherein the second oxide semiconductor layer comprises a second crystalline region having a c-axis alignment same or substantially same as that of the first crystalline region,

wherein the c-axis of the second crystalline region is aligned in a direction within ±

10°

from a perpendicular direction to a surface of the second oxide semiconductor layer, and

wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, zinc and a metal other than indium and zinc.

31. The semiconductor device according to claim 30, wherein a variation in height of the surface of the second oxide semiconductor layer is 1 nm or less in a region between the source electrode layer and the drain electrode layer.

32. The semiconductor device according to claim 30, wherein the first crystalline region included in the first oxide semiconductor layer has an average thickness greater than or equal to 2 nm and less than or equal to 10 nm.

33. The semiconductor device according to claim 30, wherein the metal comprises gallium.

34. The semiconductor device according to claim 30, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a carrier density lower than 1.0×

10¹² cm<sup>−

3</sup>.

35. The semiconductor device according to claim 30, wherein at least one of the first oxide semiconductor layer and the second oxide semiconductor layer has a hydrogen concentration lower than 5×

10¹⁹ cm<sup>−

3</sup>.

36. The semiconductor device according to claim 30, wherein a sum of thicknesses of the first oxide semiconductor layer and the second oxide semiconductor layer is greater than or equal to 3 nm and less than or equal to 50 nm.

37. The semiconductor device according to claim 30, wherein the first crystalline region of the first oxide semiconductor layer has the same electron affinity as a crystal comprised in the second oxide semiconductor layer.

38. The semiconductor device according to claim 30, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include materials including the same main component.

39. The semiconductor device according to claim 30, wherein the first oxide semiconductor layer and the second oxide semiconductor layer include different materials.

40. The semiconductor device according to claim 30, wherein portions in contact with the second oxide semiconductor layer of the source electrode layer and the drain electrode layer include a material having a low oxygen affinity.