Electronic device with controlled threshold voltage
First Claim
1. A field effect transistor having a source, drain, and a gate, comprising:
- a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried oxide layer;
a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer;
a plurality of doped regions having a predetermined dopant concentration profile in the SOI substrate, the plurality of regions including a threshold voltage set region, a screening region, and a ground plane region;
the threshold voltage set region positioned below the low-dopant channel region;
the screening region positioned in the semiconductor overlayer below the threshold voltage set region, the screening region extending between the buried insulator layer and the threshold voltage set region; and
the ground plane region positioned below the buried insulator layer.
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Accused Products
Abstract
Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.
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Citations
18 Claims
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1. A field effect transistor having a source, drain, and a gate, comprising:
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a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried oxide layer; a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer; a plurality of doped regions having a predetermined dopant concentration profile in the SOI substrate, the plurality of regions including a threshold voltage set region, a screening region, and a ground plane region; the threshold voltage set region positioned below the low-dopant channel region; the screening region positioned in the semiconductor overlayer below the threshold voltage set region, the screening region extending between the buried insulator layer and the threshold voltage set region; and the ground plane region positioned below the buried insulator layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A field effect transistor having a source, a drain, and a gate, comprising:
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a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer; a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer; and at least two regions formed by implanting dopants having a predetermined dopant concentration profile into the SOI substrate, the at least two regions including a threshold voltage set region and a ground plane region, the voltage threshold tuning region positioned in the semiconductor overlayer above the buried insulator layer, and the ground plane region positioned below the buried insulator layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18)
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Specification