Electronic device with controlled threshold voltage

• US 8,748,986 B1
• Filed: 07/26/2012
• Issued: 06/10/2014
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Shifren, Lucian, Ranade, Pushkar
• Primary Examiner(s): Blum, David S
• Application Number:
  US13/559,554
• Time in Patent Office: 684 Days
• Field of Search: 257/348, 257/384, 257/402, 257/E21.409, 257/E27.06
• US Class Current: 257/348
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Structures and methods of fabrication thereof related to an improved semiconductor on insulator (SOI) transistor formed on an SOI substrate. The improved SOI transistor includes a substantially undoped channel extending between the source and the drain, an optional threshold voltage set region positioned below the substantially undoped channel, and a screening region positioned below the threshold voltage set region. The threshold voltage of the improved SOI transistor can be adjusted without halo implants or threshold voltage implants into the channel, using the position and/or dopant concentration of the screening region and/or the threshold voltage set region.

Claims

1. A field effect transistor having a source, drain, and a gate, comprising:

a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried oxide layer;

a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer;

a plurality of doped regions having a predetermined dopant concentration profile in the SOI substrate, the plurality of regions including a threshold voltage set region, a screening region, and a ground plane region;

the threshold voltage set region positioned below the low-dopant channel region;

the screening region positioned in the semiconductor overlayer below the threshold voltage set region, the screening region extending between the buried insulator layer and the threshold voltage set region; and

the ground plane region positioned below the buried insulator layer.

2. The field effect transistor of claim 1, further comprising a predetermined dopant concentration profile having a peak dopant concentration, the peak dopant concentration being positioned in the screening region.

3. The field effect transistor of claim 2, wherein the threshold voltage set region has a doping concentration between 1/50 to ½

of the peak dopant concentration.

4. The field effect transistor of claim 2, wherein the predetermined dopant concentration profile extends through the buried insulator layer to form at least a portion of the ground plane region.

5. The field effect transistor of claim 4, wherein the ground plane region has a maximum ground plane doping concentration that is substantially equal to a maximum doping concentration of the screening region.

6. The field effect transistor of claim 2, wherein the peak dopant concentration is at least 5×

10¹⁸ atoms/cm³.

7. The field effect transistor of claim 1, wherein the screening region extends within 5 nm of the buried insulator layer.

8. The field effect transistor of claim 1, wherein the threshold voltage set region extends within 30 nm of the buried insulator layer.

9. The field effect transistor of claim 1, wherein a bias tap to the screening region is used to adjust a threshold voltage of the field effect transistor.

10. The field effect transistor of claim 1, wherein at least the semiconductor overlayer comprises silicon.

11. A field effect transistor having a source, a drain, and a gate, comprising:

a SOI substrate including a semiconductor substrate, a buried insulator layer positioned on the semiconductor substrate, and a semiconductor overlayer positioned on the buried insulator layer;

a low dopant channel region positioned below the gate and between the source and the drain, the low-dopant channel region being further positioned in an upper portion of the semiconductor overlayer; and

at least two regions formed by implanting dopants having a predetermined dopant concentration profile into the SOI substrate, the at least two regions including a threshold voltage set region and a ground plane region,

the voltage threshold tuning region positioned in the semiconductor overlayer above the buried insulator layer, and

the ground plane region positioned below the buried insulator layer.

12. The field effect transistor of claim 11, wherein the at least two regions formed by implanting dopants having the predetermined dopant concentration profile into the SOI substrate further comprises:

the predetermined dopant concentration profile having a peak dopant concentration positioned in the ground plane region, the ground plane region being formed by the dopants that penetrate through the buried insulator layer.

13. The field effect transistor of claim 12, wherein the threshold voltage set region has a doping concentration between 1/50 to ½

of the peak dopant concentration.

14. The field effect transistor of claim 12, wherein the peak dopant concentration is at least 1×

10¹⁹ atoms/cm³.

15. The field effect transistor of claim 11, wherein the threshold voltage set region extends within 30 nm of the buried insulator layer.

16. The field effect transistor of claim 11, wherein the ground plane region has at least 80 percent of the dopants in the predetermined dopant concentration profile.

17. The field effect transistor of claim 11, wherein the threshold voltage set region has less than 20 percent of the dopants in the predetermined dopant concentration profile.

18. The field effect transistor of claim 11, further including

a screening region positioned in the semiconductor overlayer below the threshold voltage set region, the screening region extending between the buried insulator layer and the threshold voltage set region;

and

a bias tap to a screening region is used to adjust a threshold voltage of the field effect transistor.