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Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices

  • US 8,748,991 B2
  • Filed: 07/17/2012
  • Issued: 06/10/2014
  • Est. Priority Date: 06/03/2009
  • Status: Active Grant
First Claim
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1. A method of forming a semiconductor structure having an n-type field effect transistor including a first patterned material stack and a p-type field effect transistor including a second patterned material stack, the method comprising:

  • providing a semiconductor substrate, the first patterned material stack formed over a first region of the substrate and the second patterned material stack formed over a second region of the substrate;

    forming an interface preparation layer in the first and second patterned material stacks;

    forming a metal nitride layer on the interface preparation layer of only the first patterned material stack;

    forming a high-k dielectric layer, having a high dielectric constant greater than approximately 3.9, on the metal nitride layer of the first patterned material stack, and on the interface preparation layer of the second patterned material stack;

    forming a Ge material layer on the high-k dielectric of both the first and second patterned material stacks; and

    forming a conductive electrode layer above the Ge material layer of both the first and second patterned material stacks.

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