Robust TSV structure

• US 8,749,027 B2
• Filed: 01/07/2009
• Issued: 06/10/2014
• Est. Priority Date: 01/07/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei, Jeng, Shin-Puu, Tu, Hung-Jung, Chiou, Wen-Chih
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US12/349,901
• Publication Number:
  US 20100171203A1
• Time in Patent Office: 1,980 Days
• Field of Search: 257/620, 257/758, 257/621
• US Class Current: 257/620
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A die includes a seal-ring structure below a substrate. The seal-ring structure is disposed around at least one substrate region. At least one means for substantially preventing ion diffusion into the substrate region. The at least one means is coupled with the seal-ring structure.

Claims

1. A die comprising:

an interconnect structure;

a substrate over the interconnect structure, the substrate having a substrate region defined therein, the substrate region being defined according to a die region of the die, the substrate being a semiconductor substrate;

a seal-ring structure in the interconnect structure positioned below the substrate, wherein, in a plan view, the seal-ring structure contacts the substrate at a location around a periphery of the die region; and

at least one means for substantially preventing ion diffusion into the substrate region, the at least one means being in direct contact with the seal-ring structure.

2. The die of claim 1, wherein the at least one means comprises a via structure.

3. The die of claim 2, wherein the via structure has a height that is substantially equal to or greater than one-half of a thickness of the substrate.

4. The die of claim 2, wherein the via structure comprises a through-silicon-via (TSV) structure.

5. The die of claim 2, wherein the substrate has at least one through-silicon-via (TSV) structure positioned within the substrate region, and the via structure comprises a plurality of vias disposed around the at least one through-silicon-via (TSV) structure.

6. The die of claim 1, wherein the substrate has at least one through-silicon-via (TSV) structure positioned within the substrate region, and the at least one means continuously extends around the at least one through-silicon-via (TSV) structure.

7. A stacked structure comprising:

a first die including

an interconnect structure;

a first substrate over the interconnect structure, the first substrate having a first substrate region defined therein, the first substrate region being defined according to a first die region of the first die, the first substrate being a first semiconductor substrate;

a first seal-ring structure in the interconnect structure positioned below the first substrate, wherein, in a plan view, the first seal-ring structure contacts the first substrate at a location around a periphery of the first die region; and

at least one first means for substantially preventing ion diffusion into the first substrate region, the at least one first means being in direct contact with the first seal-ring structure; and

a second die electrically coupled with the first die.

8. The stacked structure of claim 7, wherein the second die comprises:

a second substrate having a second substrate region defined therein, the second substrate region being defined according to a second die region of the second die, the second substrate being a second semiconductor substrate;

a second seal-ring structure positioned below the second substrate, the second seal-ring structure being around the second die region; and

at least one second means for substantially preventing ions from diffusing into the second substrate region, the at least one second means being coupled with the second seal-ring structure.

9. The stacked structure of claim 8, wherein each of the first and second means comprises a via structure.

10. The stacked structure of claim 9, wherein the via structure of the first means has a height that is substantially equal to or greater than one-half of a thickness of the first substrate, and the via structure of the second means has a height that is substantially equal to or greater than one-half of a thickness of the second substrate.

11. The stacked structure of claim 10, wherein the via structure comprises a through-silicon-via (TSV) structure.

12. The stacked structure of claim 9, wherein the first substrate has at least one through-silicon-via (TSV) structure positioned within the first substrate region, and the via structure of the first means comprises a plurality of vias disposed around the at least one through-silicon-via (TSV) structure.

13. The stacked structure of claim 8, wherein the first substrate has at least one through-silicon-via (TSV) structure positioned within the first substrate region, and the first means continuously extends around the at least one through-silicon-via (TSV) structure.

14. The stacked structure of claim 8, wherein the first die further comprises at least one first bump structure coupled with the first seal-ring structure, the second die further comprises at least one second bump structure coupled with the at least one second means, and the at least one first bump structure is coupled with the at least one second bump structure.

15. The stacked structure of claim 14, wherein at least one of the first bump structure and the second bump structure continuously extends around the first die region or the second die region.

16. The stacked structure of claim 14, wherein at least one of the first bump structure and the second bump structure includes a plurality of bumps around the first die region or the second die region.

17. The stacked structure of claim 8, wherein the at least one first seal-ring structure is spaced from the at least one second means by an underfill material.

18. A system comprising:

a substrate board; and

a stacked structure being electrically coupled with the substrate board, wherein the stacked structure comprises;

a first die comprising;

an interconnect structure;

a first substrate over the interconnect structure, the first substrate having a first substrate region defined therein, the first substrate region being defined according to a first die region of the first die, the first substrate being a first semiconductor substrate;

a first seal-ring in the interconnect structure structure positioned below the first substrate, wherein, a plan view, the first seal-ring structure contacts the first substrate at a location around a periphery of the first die region; and

at least one first means for substantially preventing ion diffusion into the first substrate region, the at least one first means being in direct contact with the first seal-ring structure; and

a second die electrically coupled with the first die.

19. The system of claim 18, wherein the second die comprises:

a second substrate having a second substrate region defined therein, the second substrate region being defined according to a second die region of the second die, the second substrate being a second semiconductor substrate;

a second seal-ring structure positioned below the second substrate, the second seal-ring structure contacting the second substrate at a location around the second die region; and

at least one second means for substantially preventing ions from diffusing into the second substrate region, the at least one second means being coupled with the second seal-ring structure.

20. The system of claim 18, wherein the at least one first means comprises a TSV structure.

21. A die comprising:

an interconnect structure;

a substrate formed over the interconnect structure, the substrate having a substrate region defined therein, the substrate region being defined according to a die region of the die, the substrate being a semiconductor substrate;

a seal-ring structure formed in the interconnect structure, wherein, in a plan view, the seal-ring structure contacts the substrate at a location around a periphery of the die region; and

a via structure formed in the substrate and in contact with the seal-ring structure.

22. The die of claim 21, wherein the via structure comprises a plurality of via structures spaced along the seal-ring structure.

23. The die of claim 21, wherein the via structure comprises a filled trench extending along the seal-ring structure.