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Semiconductor carrier with vertical power FET module

  • US 8,749,054 B2
  • Filed: 06/24/2011
  • Issued: 06/10/2014
  • Est. Priority Date: 06/24/2010
  • Status: Active Grant
First Claim
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1. A monolithic power management module, comprising:

  • a first electrode;

    a semiconductor layer disposed upon the first electrode;

    a vertical power FET formed in the semiconductor layer to modulate currents through the semiconductor layer;

    the FET having a second electrode disposed upon a surface of the semiconductor layer opposing the first electrode, and an insulated gate electrode inserted between the semiconductor layer and the first electrode; and

    a toroidal inductor with a ceramic magnetic core formed on the semiconductor layer around the FET and the inductor having a first winding around the core and connected to the FET second electrode;

    wherein windings of the toroidal inductor coil are in contact with an adjacent dielectric and comprise thin layers of electrical conductivity material that envelopes a mechanical constraining member including a low-expansion elemental metal having a measured hardness greater than 2×

    the measured hardness of the electrical conductivity material and a coefficient of thermal expansion that is within 25% of the coefficient of thermal expansion of the adjacent dielectric; and

    wherein the power FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by the charge collected beneath the gate, a resistive element determined by the conductor, length and cross-sectional area of the conductor used to form the serpentine gate electrode, and an inductive element formed by the half-turns that loop the serpentine winding back upon itself.

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