Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a memory cell unit comprising a plurality of memory elements;
a first transistor comprising a first terminal, a second terminal, and a gate;
an inverted data output circuit comprising an input terminal and an output terminal, wherein the input terminal is electrically connected to the first terminal of the first transistor and the output terminal is electrically connected to the memory cell unit and the second terminal of the first transistor; and
a capacitor electrically connected to the input terminal of the inverted data output circuit and the first terminal of the first transistor.
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Accused Products
Abstract
An object is to provide a semiconductor memory device capable of copying memory data without using an external circuit. The semiconductor memory device includes a bit line to which first terminals of a plurality of memory cells are connected in common; a pre-charge circuit which is connected to the bit line and pre-charges the bit line with a specific potential in data reading; a data holding circuit comprising a capacitor which temporarily holds data read out from the memory cell or data which is written to the memory cell; and an inverted data output circuit which outputs inverted data of data held in the data holding circuit to the bit line. The inverted data output circuit includes a means for controlling output of inverted data of data held in the data holding circuit.
112 Citations
22 Claims
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1. A semiconductor memory device comprising:
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a memory cell unit comprising a plurality of memory elements; a first transistor comprising a first terminal, a second terminal, and a gate; an inverted data output circuit comprising an input terminal and an output terminal, wherein the input terminal is electrically connected to the first terminal of the first transistor and the output terminal is electrically connected to the memory cell unit and the second terminal of the first transistor; and a capacitor electrically connected to the input terminal of the inverted data output circuit and the first terminal of the first transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor memory device comprising:
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a memory cell unit comprising a plurality of memory elements; a first transistor comprising a first terminal, a second terminal, and a gate; an inverted data output circuit comprising a three-state inverter circuit comprising an input terminal and an output terminal, wherein the input terminal is electrically connected to the first terminal of the first transistor and the output terminal is electrically connected to the memory cell unit and the second terminal of the first transistor; and a capacitor electrically connected to the input terminal of the three-state inverter circuit and the first terminal of the first transistor. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A semiconductor memory device comprising:
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a memory cell unit comprising a plurality of memory elements; a first transistor comprising a first terminal, a second terminal, and a first gate; an inverted data output circuit comprising; an inverter comprising an input terminal and an output terminal, wherein the input terminal is electrically connected to the first terminal of the first transistor; and a second transistor comprising a third terminal, a fourth terminal, and a second gate, wherein the third terminal is electrically connected to the output terminal of the inverter and the fourth terminal is electrically connected to the memory cell unit and the second terminal of the first transistor; and a capacitor electrically connected to the input terminal of the inverter and the first terminal of the first transistor. - View Dependent Claims (17, 18, 19, 20, 21, 22)
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Specification