Data cells with drivers and methods of making and operating the same

• US 8,750,025 B2
• Filed: 08/13/2013
• Issued: 06/10/2014
• Est. Priority Date: 04/03/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/965,488
• Publication Number:
  US 20130329486A1
• Time in Patent Office: 301 Days
• Field of Search: 365/149, 365/174
• US Class Current: 365/149
• CPC Class Codes: G11C 11/40 using transistors
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: H10B 12/34 the transistor being at least partially in a trench in the substrate
• CPC Class Codes: H10B 12/36 the transistor being a FinFET

Abstract

Disclosed are methods and devices, among which is a device that includes a first semiconductor fin having a first gate, a second semiconductor fin adjacent the first semiconductor fin and having a second gate, and a third gate extending between the first semiconductor fin and the second semiconductor fin. In some embodiments, the third gate may not be electrically connected to the first gate or the second gate.

Claims

1. A circuit, comprising:

a plurality of data cells individually comprising;

a data element; and

a driver connected to the data element;

the driver comprising first, second, and third transistors;

a gate of the third transistor extending under a gate of the first transistor and a gate of the second transistor.

2. The circuit of claim 1, wherein the data element comprises a memory element or an imaging element.

3. The circuit of claim 1, wherein the data element comprises a capacitor.

8. The circuit of claim 1, wherein the gate of the third transistor is longitudinally elongated perpendicularly relative to longitudinal orientation of at least one of the gate of the first transistor and the gate of the second transistor.

9. The circuit of claim 8, wherein the gates of the first and second transistors are longitudinally elongated parallel relative one another and the gate of the third transistor is longitudinally elongated perpendicularly relative to longitudinal orientations of each of the gates of the first and second transistors.

10. The circuit of claim 1, wherein the first transistor comprises a pair of spaced gates.

11. The circuit of claim 10, wherein the spaced gates are longitudinally elongated parallel relative one another.

12. The circuit of claim 1, wherein the second transistor comprises a pair of spaced gates.

13. The circuit of claim 12, wherein the spaced gates are longitudinally elongated parallel relative one another.

14. The circuit of claim 12, wherein the first transistor comprises a pair of spaced gates.

15. The circuit of claim 14, wherein the spaced gates of the first transistor and the spaced gates of the second transistor are all longitudinally elongated parallel relative one another.

16. The circuit of claim 15, wherein the gate of the third transistor is longitudinally elongated perpendicularly relative to longitudinal orientations of the spaced gates of each of the first and second transistors.

17. The circuit of claim 15, wherein the gates of the first and second transistors are electrically coupled to one another.

18. The circuit of claim 17, wherein the gate of the third transistor is not electrically coupled to any of the gates of the first and second transistors.

19. The circuit of claim 18, wherein the gates of the first and second transistors are electrically coupled to one another.

4. A method, comprising:

storing data by changing a voltage of a capacitor;

applying the voltage of the capacitor to a first gate of a first fin field-effect transistor;

controlling a current through the first fin field-effect transistor at least in part according to the voltage of the first gate; and

reading the stored data by measuring the current or a change in voltage produced by the current.

5. The method of claim 4, comprising applying a read voltage to a second gate of the first fin field-effect transistor.

6. The method of claim 4, wherein storing data comprises conducting a second current through a second fin field-effect transistor.

7. The method of claim 6, wherein applying the voltage of the capacitor to the first gate of the fin field-effect transistor comprises propagating the voltage through a conductor that extends between the first fin field-effect transistor and the second fin field-effect transistor, under the second gate of the first fin field-effect transistor.

20. A circuit, comprising:

a plurality of data cells individually comprising;

a data element; and

a driver connected to the data element;

the driver comprising first, second, and third transistors;

a gate of the third transistor comprising a buried member having two risers projecting upwardly therefrom.

21. The circuit of claim 20, wherein the two risers project vertically and perpendicularly from the buried member.

22. The circuit of claim 21, wherein one of the two risers comprises a lip extending perpendicularly therefrom.

23. A circuit, comprising:

a plurality of data cells individually comprising;

a data element;

a driver connected to the data element, the driver comprising;

first, second, and third transistors;

gates of the first and second transistors being electrically coupled to one another;

no gate of the third transistor being electrically coupled to any gate of the first transistor nor being electrically coupled to any gate of the second transistor;

one source/drain of the third transistor being electrically coupled to one source/drain of one of the first and second transistors;

another source/drain of the third transistor being electrically coupled to one source/drain of the other of the first and second transistors;

a gate of the third transistor being electrically coupled to the data element; and

a fourth transistor having one of its source/drains electrically coupled to the data element.

24. The circuit of claim 23, wherein the driver has no more transistors than said first, second, and third transistors.

25. The circuit of claim 23, wherein the data element comprises a memory element or an imaging element.

26. The circuit of claim 23, wherein the data element comprises a capacitor.