Data storage device and control method for non-volatile memory

• US 8,750,043 B2
• Filed: 08/16/2012
• Issued: 06/10/2014
• Est. Priority Date: 08/16/2012
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Su, Teng, Huang, Koying, Chan, Johnny
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/587,158
• Publication Number:
  US 20140050041A1
• Time in Patent Office: 663 Days
• Field of Search: 365/185.11, 365/185.12, 365/185.29, 365/185.22, 365/185.23
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

A data storage device having a non-volatile memory and a controller and a control method for the non-volatile memory are disclosed. The non-volatile memory has a plurality of blocks for data storage and each block provides a plurality of sectors. The controller allocates erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required.

Claims

1. A data storage device, comprising:

a non-volatile memory, comprising a plurality of blocks for data storage, wherein each block provides a plurality of sectors; and

a controller, allocating erase marker bits in each of the sectors to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required,

wherein the erase operation includes a pre-program process, an erase process, a post program process and a refresh process which are differentiated by different values of the erase marker bits.

2. The data storage device as claimed in claim 1, wherein when a sector erase operation is being performed on one sector, the controller changes the erase marker bits of the one sector.

3. The data storage device as claimed in claim 2, wherein when a block erase operation is performed on one block the controller changes the erase marker bits of at least two sectors of the one block.

4. The data storage device as claimed in claim 3, wherein:

during an erase operation resumption process, the controller resumes a block erase operation on a block under verification when determining that more than one sector of the block under verification contains changed erase marker bits.

5. The data storage device as claimed in claim 4, wherein when determining that the block under verification only has one sector containing changed erase marker bits the controller resumes a sector erase operation on the one sector within the block under verification.

6. The data storage device as claimed in claim 5, wherein:

during the erase operation resumption process, the controller verifies the blocks of the non-volatile memory one by one till changed erase marker bits are detected or all blocks of the non-volatile memory are verified.

7. The data storage device as claimed in claim 5, wherein the controller uses several values to set the erase marker bits and the several values are:

a first value, indicating a pre-program status;

a second value, indicating an erase status;

a third value, indicating a post-program status;

a fourth value, indicating a refresh status; and

a fifth value, a default value for the erase marker bits, indicating an erase-done status.

8. A control method for a non-volatile memory having a plurality of blocks for data storage, wherein each block provides a plurality of sectors, comprising:

allocating erase marker bits in each of the sectors; and

using the erase marker bits to record the progress of an erase operation performed on the non-volatile memory for resumption of the erase operation when required,

wherein the erase operation includes a pre-program process, an erase process, a post program process and a refresh process which are differentiated by different values of the erase marker bits.

9. The control method as claimed in claim 8, further comprising:

changing the erase marker bits of one sector when a sector erase operation is performed on the one sector.

10. The control method as claimed in claim 9, further comprising:

changing the erase marker bits of at least two sectors of one block when a block erase operation is performed on the one block.

11. The control method as claimed in claim 10, further comprising:

during an erase operation resumption process, resuming a block erase operation on a block under verification when more than one sector of the block under verification is determined to contain changed erase marker bits.

12. The control method as claimed in claim 11, wherein:

when it is determined that the block under verification only has one sector containing changed erase marker bits, a sector erase operation is resumed on the one sector within the block under verification.

13. The control method as claimed in claim 12, wherein during the erase operation resumption process the blocks of the non-volatile memory are verified one by one till changed erase marker bits are detected or all blocks of the non-volatile memory are verified.

14. The control method as claimed in claim 12, further comprising:

using several values to set the erase marker bits,

where the several values are;

a first value, indicating a pre-program status;

a second value, indicating an erase status;

a third value, indicating a post-program status;

a fourth value, indicating a refresh status; and

a fifth value, a default value for the marker bits, indicating an erase-done status.