Experience count dependent program algorithm for flash memory

• US 8,750,045 B2
• Filed: 07/27/2012
• Issued: 06/10/2014
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Huang, Jianmin, Tanpairoj, Kulachet, Avila, Chris Nga Yee, Dusija, Gautam Ashok
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/560,896
• Publication Number:
  US 20140029342A1
• Time in Patent Office: 683 Days
• Field of Search: 365/185.22, 365/185.19, 365/185.29, 365/185.11, 365/185.14, 365/185.33, 365/189.04
• US Class Current: 365/185.12
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically

Abstract

In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.

Claims

1. A method of providing one or more non-volatile memory circuits, comprising:

manufacturing multiple non-volatile memory chips according to the same design;

for each of a plurality of the memory chips, individually characterizing the voltage waveforms produced by the memory chip for a state changing operation on memory cells of the memory chip;

for each of the plurality of the memory chips, individually trimming the voltage waveforms based upon the corresponding individual characterizations;

using a set of one or more, but less than all, of the manufactured memory chips, determining an amount of variation in device characteristics for said state changing operation for a plurality of distinct age ranges, the plurality of age ranges including a first range, that includes when the memory chips of the set are fresh, and one or more second ranges;

based on the amount of variation in device characteristics, determining an offset for one or more values for parameters for the state changing operation for each of the one or more second ranges relative to the first range; and

storing the one or more offsets on each of the plurality of non-volatile memory chips.

2. The method of claim 1, wherein the state changing operation is an erase operation.

3. The method of claim 1, wherein the state changing operation is a program operation.

4. The method of claim 1, wherein the voltage waveforms includes a series of pulses forming a staircase of increasing amplitude.

5. The method of claim 4, wherein the staircase has uniform step size and the trimming includes setting the amplitude of the initial pulse of the staircase.

6. The method of claim 4, wherein the offsets include an offset for the amplitude of the initial pulse of the staircase.

7. The method of claim 6, wherein the offsets include a shift in the maximum number of allowed pulses for the staircase.

8. The method of claim 1, further comprising:

subsequently forming one or more of said plurality of non-volatile memory chips and a controller chip into a non-volatile memory system.

9. The method of claim 8, where the non-volatile memory system is a memory card.

10. The method of claim 8, where the non-volatile memory system is a solid state drive.