Self-repairing memory
First Claim
1. A memory structure comprising:
- a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;
a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;
a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array;
a plurality of second bits, each second bit of the plurality of second bits associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit; and
an error correction engine configuredto generate an error-repair flag based on the logic state of a corresponding first bit associated with a memory word and presence of an error in the memory word;
orto generate the error-repair flag based on the logic state of a corresponding second bit associated with a redundancy word and presence of an error in the redundancy word.
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Accused Products
Abstract
A memory array has a plurality of rows. Each row of the plurality of rows includes a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the memory word associated the each first bit has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. Each second bit of a plurality of second bits is associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows. A state of the each second bit indicates whether the redundancy word associated with the each second bit has had an error.
17 Citations
22 Claims
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1. A memory structure comprising:
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a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words; a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit; a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array; a plurality of second bits, each second bit of the plurality of second bits associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit; and an error correction engine configured to generate an error-repair flag based on the logic state of a corresponding first bit associated with a memory word and presence of an error in the memory word;
orto generate the error-repair flag based on the logic state of a corresponding second bit associated with a redundancy word and presence of an error in the redundancy word. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A memory structure comprising:
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a memory row of a memory array, the memory row including a plurality of memory words; a plurality of first bits, each first bit of the plurality of first bits associated with each memory word of the plurality of memory words of the memory row; an error correction engine configured to generate an error-repair flag based on a state of a first bit associated with a memory word and an error of the memory word; and a repair engine configured to repair the memory word having the error based on the error-repair flag. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method comprising:
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accessing a data word and a data bit associated with the data word; and in response to an error in accessing the data word, performing at least one of the following groups of steps; based on a first state of the data bit, changing a state of the data bit; and writing correct data to the data word; and based on a second state of the data bit, generating an error-fixing flag for use in repairing the data word, wherein the first state of the data bit indicates the data word had no other error prior to having the error in accessing the data word; and the second state of the data bit indicates the data word had another error prior to having the error in accessing the data word. - View Dependent Claims (18, 19, 20, 21, 22)
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Specification