Self-repairing memory

• US 8,750,059 B2
• Filed: 02/17/2012
• Issued: 06/10/2014
• Est. Priority Date: 08/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: O'Connell, Cormac Michael
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): Yang, Han
• Application Number:
  US13/399,993
• Publication Number:
  US 20130215695A1
• Time in Patent Office: 844 Days
• Field of Search: 365/200, 365/185.09, 365/201, 365/230.01
• US Class Current: 365/200
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/808 using a flexible replacement scheme

Abstract

A memory array has a plurality of rows. Each row of the plurality of rows includes a plurality of memory words. Each first bit of a plurality of first bits is associated with a memory word of the each row. A state of the each first bit indicates whether the memory word associated the each first bit has had an error. Each redundancy row of a plurality of redundancy rows includes a plurality of redundancy words. Each redundancy word is associated with a memory word. Each second bit of a plurality of second bits is associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows. A state of the each second bit indicates whether the redundancy word associated with the each second bit has had an error.

Claims

1. A memory structure comprising:

a memory array having a plurality of rows, each row of the plurality of rows of the memory array including a plurality of memory words;

a plurality of first bits, each first bit of the plurality of first bits associated with a memory word of the plurality of memory words of the each row of the plurality of rows of the memory array, wherein a logic state of the each first bit indicates whether the memory word associated with the each first bit has had a failed bit;

a plurality of redundancy rows, each redundancy row of the plurality of redundancy rows including a plurality of redundancy words, each redundancy word of the plurality of redundancy words associated with a corresponding memory word of the plurality of memory words of the each row of the plurality of rows of the memory array;

a plurality of second bits, each second bit of the plurality of second bits associated with a redundancy word of the plurality of redundancy words of the each row of the plurality of redundancy rows, wherein a logic state of the each second bit indicates whether the redundancy word associated with the each second bit has had a failed bit; and

an error correction engine configured

to generate an error-repair flag based on the logic state of a corresponding first bit associated with a memory word and presence of an error in the memory word;

or

to generate the error-repair flag based on the logic state of a corresponding second bit associated with a redundancy word and presence of an error in the redundancy word.

2. The memory structure of claim 1, further comprising:

a word logic engine configured to process each memory word of the plurality of memory words of a row of the memory array; and

a bit-tag logic engine configured to process the each first bit associated with the each memory word of the plurality of memory words to be processed.

3. The memory structure of claim 1, wherein the memory structure is configured to satisfy at least one of the following conditions:

the each first bit is associated with the memory word based on a first index of the each first bit and a second index of the memory word associated with the each first bit;

or

the each second bit is associated with the redundancy word based on a third index of the each second bit and a fourth index of the redundancy word associated with the each second bit.

4. The memory structure of claim 1, wherein the memory structure is configured to satisfy at least one of the following conditions:

the plurality of first bits is associated with the plurality of memory words based on a first combinational logic;

or

the plurality of second bits is associated with the plurality of redundancy word based on a second combinational logic.

5. The memory structure of claim 1, wherein the error correction engine is further configured

to maintain the logic state of the corresponding first bit associated with the memory word when accessing the memory word does not cause an indication of the presence of an error in the memory word;

or

to maintain the logic state of the corresponding second bit associated with the redundancy word when accessing the redundancy word does not cause an indication of the presence of an error in the redundancy word.

6. The memory structure of claim 1, wherein the error correction engine is further configured

to cause a change in the logic state of the corresponding first bit associated with the memory word when accessing the memory word causes the indication of the presence of an error in the memory word;

or

to cause a change in the logic state of the corresponding second bit associated with the redundancy word when accessing the redundancy word causes the indication of the presence of an error in the redundancy word.

7. The memory structure of claim 1, wherein the error-repair flag is for use in at least one of the following situations:

to trigger a repair of the memory word associated with the corresponding first bit;

or

to trigger a repair of the redundancy word associated with the corresponding second bit.

8. The memory structure of claim 1, wherein

a first redundancy row of the plurality of redundancy of rows is configured to be used in place of a row of the memory array or in place of a second redundancy row.

9. The memory structure of claim 1, wherein

a first redundancy word of the plurality of redundancy rows is configured to be used in place of a word of the memory array or in place of a second word of the plurality of redundancy rows.

10. A memory structure comprising:

a memory row of a memory array, the memory row including a plurality of memory words;

a plurality of first bits, each first bit of the plurality of first bits associated with each memory word of the plurality of memory words of the memory row;

an error correction engine configured to generate an error-repair flag based on a state of a first bit associated with a memory word and an error of the memory word; and

a repair engine configured to repair the memory word having the error based on the error-repair flag.

11. The memory structure of claim 10 further comprising:

a first redundancy row, wherein the first redundancy row includes a plurality of first redundancy words, each first redundancy word of the plurality of first redundancy words is associated with the each memory word of the plurality of memory words of the memory row; and

a plurality of second bits, wherein each second bit of the plurality of second bits is associated with the each first redundancy word of the plurality of first redundancy words, a state of the each second bit indicates whether the each first redundancy word associated with the each second bit has had an error in the each first redundancy word.

12. The memory structure of claim 11, wherein

the first redundancy row is configured to be used in place of the memory row;

or

a redundancy word of the first redundancy row is configured to be used in place of a word of the memory row.

13. The memory structure of claim 11, further comprising:

a second redundancy row, wherein the second redundancy row includes a plurality of second redundancy words, each second redundancy word of the plurality of second redundancy words is associated with the each memory word of the plurality of memory words; and

a plurality of third bits, wherein each third bit of the plurality of third bits is associated with each second redundancy word of the plurality of second redundancy words, a state of the each third bit indicates whether the each second redundancy word associated with the each third bit has had an error in the each second redundancy word.

14. The memory structure of claim 13, wherein

the second redundancy row is configured to be used in place of the first redundancy row;

or

a word of the second redundancy row is configured to be used in place of a word of the first redundancy row.

15. The memory structure of claim 10, further comprising a queue configured to store data related to the memory word having the error.

16. The memory structure of claim 10, wherein the repair engine is configured to repair the memory word having the error further based on a NOP instruction of a system using the memory structure.

17. A method comprising:

accessing a data word and a data bit associated with the data word; and

in response to an error in accessing the data word, performing at least one of the following groups of steps;

based on a first state of the data bit,

changing a state of the data bit; and

writing correct data to the data word; and

based on a second state of the data bit,

generating an error-fixing flag for use in repairing the data word,

wherein

the first state of the data bit indicates the data word had no other error prior to having the error in accessing the data word; and

the second state of the data bit indicates the data word had another error prior to having the error in accessing the data word.

18. The method of claim 17, wherein

the memory row is a part of a memory array or a part of a redundancy memory array.

19. The method of claim 17, wherein the error-fixing flag indicates one or a combination of the following:

the data word is to be repaired;

or

a NOP instruction is requested so that the data word is repaired.

20. The method of claim 17, wherein repairing the data word comprises using a NOP instruction.

21. The method of claim 17, further comprising:

copying data of a row having the data word to a redundancy row that has a plurality of redundancy words, each redundancy word of the plurality of redundancy words corresponding to a redundancy data bit; and

setting the redundancy data bit corresponding to the each redundancy word of the plurality of redundancy words to a state indicating that the each redundancy word had no previous error.

22. The method of claim 21, further comprising the step of redirecting another access of the data word to the redundancy row or to a word of the redundancy row.