Multi-level amplitude signaling receiver

• US 8,750,406 B2
• Filed: 01/31/2012
• Issued: 06/10/2014
• Est. Priority Date: 01/31/2012
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Pan, Mingde, Ding, Weiqi, Shumarayev, Sergey, Li, Peng, Shimanouchi, Masashi
• Primary Examiner(s): WANG, TED M
• Application Number:
  US13/363,098
• Publication Number:
  US 20130195155A1
• Time in Patent Office: 861 Days
• Field of Search: 375/287, 375/316, 375/286, 375/324, 375/340
• US Class Current: 375/287
• CPC Class Codes: H03D 1/00 Demodulation of amplitude-modulated oscillations H03D5/00, H03D9/00, H03D11/00 take precedence
• CPC Class Codes: H04L 25/066 Multilevel decisions, not including self-organising maps
• CPC Class Codes: H04L 25/4917 using multilevel codes
• CPC Class Codes: H04L 27/06 Demodulator circuits; Receiver circuits

Abstract

One embodiment relates to a receiver circuit for multi-level amplitude signaling which includes at least three amplitude levels for each symbol period. The receiver circuit includes a peak detector, a reference voltage generator, and a comparator circuit. The peak detector is arranged to detect a peak voltage of the multi-level amplitude signal, and the reference voltage generator uses the peak voltage to generate multiple reference voltages. The comparator circuit uses the multiple reference voltages to detect an amplitude level of the multi-level amplitude signal. Other embodiments and features are also disclosed.

Claims

1. A receiver circuit for multi-level amplitude signaling, the receiver circuit comprising:

a peak detector for detecting a peak voltage of a multi-level amplitude signal which includes at least three amplitude levels for each symbol period;

a reference voltage generator for generating a plurality of reference voltages at least partially in response to the peak voltage; and

a comparator circuit which uses the plurality of reference voltages to detect an amplitude level of the multi-level amplitude signal,

wherein a number of comparators in the comparator circuit is less than a number of amplitude levels in the multi-level amplitude signal.

2. The receiver circuit of claim 1, wherein the multi-level amplitude signal comprises a three-level pulse amplitude modulated (PAM-3) signal, and wherein the comparator circuit comprises less than three comparators.

3. The receiver circuit of claim 1, wherein the multi-level amplitude signal comprises a four-level pulse amplitude modulated (PAM-4) signal, and wherein the comparator circuit comprises less than four comparators.

4. A receiver circuit for multi-level amplitude signaling, the receiver circuit comprising:

a peak detector for detecting a peak voltage of a multi-level amplitude signal which includes at least three amplitude levels for each symbol period;

a reference voltage generator for generating a plurality of reference voltages at least partially in response to the peak voltage; and

a comparator circuit which uses the plurality of reference voltages to detect an amplitude level of the multi-level amplitude signal,

wherein the reference voltage generator comprises an inverting amplifier that includes at least one resistor ladder.

5. The receiver circuit of claim 4, wherein a reference voltage is obtained from a node in the resistor ladder.

6. The receiver circuit of claim 5, wherein selection of the node is programmable.

7. A method of receiving a multi-level amplitude signal, the method comprising:

detecting a peak voltage of a multi-level amplitude signal by a peak detector circuit, wherein the multiple-level amplitude signal includes at least three amplitude levels for each symbol period;

generating a plurality of reference voltages by a reference voltage generator circuit, wherein the plurality of reference voltages are at least partially responsive to the peak voltage; and

comparing the multi-level amplitude signal against the plurality of reference voltages by a comparator circuit to detect an amplitude level,

wherein the comparing is performed by a number of comparators that is less than a number of amplitude levels in the multi-level amplitude signal.

8. The method of claim 7, wherein the multi-level amplitude signal comprises a three-level pulse amplitude modulated (PAM-3) signal, and wherein the comparator comparing is performed by less than three comparators.

9. The method of claim 7, wherein the multi-level amplitude signal comprises a four-level pulse amplitude modulated (PAM-4) signal, and wherein the comparing is performed by less than four comparators.

10. A method of receiving a multi-level amplitude signal, the method comprising:

detecting a peak voltage of a multi-level amplitude signal by a peak detector circuit, wherein the multiple-level amplitude signal includes at least three amplitude levels for each symbol period;

generating a plurality of reference voltages by a reference voltage generator circuit, wherein the plurality of reference voltages are at least partially responsive to the peak voltage; and

comparing the multi-level amplitude signal against the plurality of reference voltages by a comparator circuit to detect an amplitude level,

wherein the plurality of reference voltages are generated using an inverting amplifier that includes at least one resistor ladder.

11. The method of claim 10, further comprising:

obtaining a reference voltage from a node in the resistor ladder.

12. An integrated circuit comprising:

a pulse amplitude modulation receiver which includes

a peak detector arranged to detect a peak voltage of a transmitted pulse amplitude modulation signal which includes at least three amplitude levels for each symbol period,

a reference voltage generator arranged to generate a plurality of reference voltages which depend on the peak voltage, and

a comparator circuit arranged to compare the pulse amplitude modulation signal against the plurality of reference voltages to detect an amplitude level; and

a transmitter which includes

a serializer arranged to convert a parallel data signal to a serial data signal,

a coder arranged to encode the serial data signal so as to generate a plurality of code bits, and

a driver arranged to use the plurality of code bits to generate a pulse amplitude modulation signal for transmission.