Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
First Claim
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1. A digital signal processing (“
- DSP”
) circuit block comprising;
first multiplier circuitry that performs a first multiplication of two inputs each of a first size;
second multiplier circuitry that performs a selectable one of (1) a second multiplication of two inputs each of the first size and (2) a multiplication of a first input of a second size smaller than the first size by a second input of a third size larger than the first size and a multiplication of a third input of the second size by a fourth input of the first size;
shifting circuitry that shifts outputs of the first multiplier circuitry by a selectable one of (1) zero bit positions and (2) a number of bit positions, equal to the first size, toward greater arithmetic significance;
first addition circuitry that additively combines outputs of the second multiplier circuitry and the shifting circuitry;
first routing circuitry that routes outputs of the first addition circuitry to a first other DSP circuit block; and
second addition circuitry that additively combines outputs of the first addition circuitry and outputs received from a second other DSP circuit block.
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Abstract
Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.
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Citations
10 Claims
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1. A digital signal processing (“
- DSP”
) circuit block comprising;first multiplier circuitry that performs a first multiplication of two inputs each of a first size; second multiplier circuitry that performs a selectable one of (1) a second multiplication of two inputs each of the first size and (2) a multiplication of a first input of a second size smaller than the first size by a second input of a third size larger than the first size and a multiplication of a third input of the second size by a fourth input of the first size; shifting circuitry that shifts outputs of the first multiplier circuitry by a selectable one of (1) zero bit positions and (2) a number of bit positions, equal to the first size, toward greater arithmetic significance; first addition circuitry that additively combines outputs of the second multiplier circuitry and the shifting circuitry; first routing circuitry that routes outputs of the first addition circuitry to a first other DSP circuit block; and second addition circuitry that additively combines outputs of the first addition circuitry and outputs received from a second other DSP circuit block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- DSP”
Specification