Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry

• US 8,751,551 B2
• Filed: 11/21/2013
• Issued: 06/10/2014
• Est. Priority Date: 03/03/2009
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Streicher, Keone, Langhammer, Martin, Lin, Yi-Wen, Leung, Wai-Bor, Lewis, David, Mauer, Volker, Lui, Henry Y., Demirsoy, Suleyman Sirri, Yi, Hyun
• Primary Examiner(s): SUN, SCOTT C
• Application Number:
  US14/086,328
• Publication Number:
  US 20140082035A1
• Time in Patent Office: 201 Days
• Field of Search: None
• US Class Current: 708/230
• CPC Class Codes: G06F 17/10 Complex mathematical operations function generation by table look-up G06F1/03; evaluation of elementary functions by calculation G06F7/544
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 7/5324 partitioned, i.e. using repetitively a smaller parallel parallel multiplier or using an array of such smaller multipliers
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H03H 2220/06 Systolic
• CPC Class Codes: H03K 19/17732 Macroblocks

Abstract

Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Claims

1. A digital signal processing (“

DSP”

) circuit block comprising;

first multiplier circuitry that performs a first multiplication of two inputs each of a first size;

second multiplier circuitry that performs a selectable one of (1) a second multiplication of two inputs each of the first size and (2) a multiplication of a first input of a second size smaller than the first size by a second input of a third size larger than the first size and a multiplication of a third input of the second size by a fourth input of the first size;

shifting circuitry that shifts outputs of the first multiplier circuitry by a selectable one of (1) zero bit positions and (2) a number of bit positions, equal to the first size, toward greater arithmetic significance;

first addition circuitry that additively combines outputs of the second multiplier circuitry and the shifting circuitry;

first routing circuitry that routes outputs of the first addition circuitry to a first other DSP circuit block; and

second addition circuitry that additively combines outputs of the first addition circuitry and outputs received from a second other DSP circuit block.

2. The DSP circuit block defined in claim 1 wherein the second multiplier circuitry comprises:

third multiplier circuitry that performs the multiplication of the first input of the second size by the second input of the third size;

fourth multiplier circuitry that performs the multiplication of the third input of the second size by the fourth input of the first size; and

third addition circuitry that additively combines outputs of the third multiplier circuitry and the fourth multiplier circuitry, with bits of the outputs of the fourth multiplier circuitry being increased in arithmetic significance by number of bit positions equal to the second size relative to bits of the outputs of the third multiplier circuitry.

3. The DSP circuit block defined in claim 2 further comprising:

second routing circuitry that selectively routes a number, equal to the first size, of the most significant bits of a multiplicand data word of the third size to multiplicand inputs to the first multiplier circuitry;

third routing circuitry that selectively routes a number, equal to the first size, of the most significant bits of a multiplier data word of the third size to multiplier inputs to the first multiplier circuitry;

fourth routing circuitry that selectively routes the multiplicand of the third size to the multiplicand inputs to the third multiplier circuitry;

fifth routing circuitry that selectively routes a number, equal to the second size, of the least significant bits of the multiplier data word to multiplier inputs to the third multiplier circuitry;

sixth routing circuitry that selectively routes a number, equal to the first size, of the most significant bits of the multiplier data word to multiplicand inputs to the fourth multiplier circuitry; and

sixth routing circuitry that selectively routes a number, equal to the second size, of the least significant bits of the multiplicand data word to the multiplier inputs to the fourth multiplier circuitry.

4. The DSP circuit block defined in claim 1 further comprising:

respective groups of multiple conductors for respectively receiving respective multiple pluralities of data input signals for use as inputs to the first multiplier circuitry and the second multiplier circuitry;

pre-adder circuitry that selectively pre-adds at least some of the data input signals; and

selection circuitry that selectively applies outputs of the pre-adder circuitry to selected inputs to at least one of the first multiplier circuitry and the second multiplier circuitry.

5. The DSP circuit block defined in claim 1 further comprising:

selectively usable systolic register circuitry in input data signal paths of the second multiplier circuitry for selectively giving inputs to the second multiplier circuitry a systolic register delay.

6. The DSP circuit block defined in claim 1 wherein the first routing circuitry comprises:

first shifting circuitry that shifts the outputs of the first addition circuitry by a selectable one of (1) zero bit positions and (2) a number, equal to the first size, of bit positions toward lesser arithmetic significance.

7. The DSP circuit block defined in claim 1 wherein the first routing circuitry comprises:

seventh routing circuitry that selectively alternatively routes output signals indicative of outputs of the second addition circuitry to the first other DSP circuit block.

8. The DSP circuit block defined in claim 7 wherein the seventh routing circuitry comprises:

selectively usable systolic register circuitry that selectively gives the output signals indicative of outputs of the second addition circuitry a systolic register delay.

9. The DSP circuit block defined in claim 1 wherein the first routing circuitry comprises:

eighth routing circuitry that alternatively routes signals from the second other DSP circuit block to the first other DSP circuit block.

10. The DSP circuit block defined in claim 1 wherein the second addition circuitry comprises:

registers for output signals indicative of outputs of the second addition circuitry; and

ninth routing circuitry for applying outputs of the registers to inputs to the second addition circuitry.